ST78C34CP40 datasheet(6/21 Pages) EXAR

Nome de Peças	ST78C34CP40

Descrição Electrónicos	GENERAL PURPOSE PARALLEL PRINTER PORT WITH 83 BYTE FIFO

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Fabricante Electrônico	EXAR [Exar Corporation]

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6-8

ST78C34

Rev. 3.00

PRINTER PORT PROGRAMMING TABLE:

A1

A0

WRITE MODE

READ MODE

0

PORT REGISTER

0

1

STATUS REGISTER *

1

0

CONTROL REGISTER

COMMAND REGISTER

1

ALTERNATE FUNCTION REGISTER

FIFO BYTE COUNT REGISTER

* Reading the status register will reset the INT output.

PRINTER FUNCTIONAL DESCRIPTION

The ST78C34 parallel port is designed to operate as

a normal CENTRONICS printer interface. The port

contains 83 byte FIFO that may be enabled via bit-7

of the Alternate Function Register (AFR). After reset,

the FIFO is disabled and the part will function identical

to the ST16C552. Once the FIFO is enabled via AFR

bit-7, the port will enter FIFO mode after the first byte

of data is strobed to the printer and the printer re-

sponds with either an -ACK or BUSY signal.

The ST78C34 will remain in FIFO mode until the part

is reset or INIT is brought low. While in FIFO mode,

data transfer to the printer will be controlled by the

printer without any user intervention. The printer port

also contains a FIFO byte counter that maintains a

count of the number of bytes remaining in the FIFO.

The FIFO and the FIFO byte counter are cleared by a

reset or by a change of state of the INIT pin. All FIFO

related timing is derived from the clock input to pin 17

of the part.

A special parallel port write / read mode is activated

when INIT is held low, either by writing a “0” to Control

Register bit-2 or by forcing the INIT pin low. In this

mode the FIFO read pointer is advanced by reading

the parallel port instead of the -ACK or BUSY signals.

The -STROBE output is forced high. This allows the

user to perform parallel port write and read from

operations without strobing data to the printer.

Following an INIT, the parallel port will not be in the

FIFO mode. Control Register bit-0 is used as the -

STROBE, Status Register bit-7 is the inverse of the

BUSY signal, and INT is derived from -ACK. The

transition into FIFO mode will occur after the first -

STROBE is generated and the printer responds with

either an -ACK or BUSY. In FIFO mode, -STROBE is

generated automatically and writing to Control Regis-

ter bit-0 has no effect on -STROBE. Alternate Func-

tion Register bit 0-2 are used to control the delay and

width of -STROBE. Handshaking between the printer

and the ST78C34 may be controlled by bit-3 of the

Alternate Function Register. Setting this bit to a “1” will

result in the use of BUSY instead of -ACK for FIFO

reading and interrupt control. INT will transition low

when a “1” is written to Control Register bit-0 and will

transition high when a write to parallel port is per-

formed. In FIFO mode, data transfer to the printer will

be controlled by the printer and will occur at the

printer’s maximum data rate.

The FIFO byte counter is incremented one count for

each parallel port write and decremented one count

for each FIFO read (data taken by printer). A FIFO

read will be generated at the falling edge of either -

ACK or BUSY. The byte counter will require two to

three clock cycles to update. Hence, a read of FIFO

Byte Count Register (FBCR) should only be per-

formed a minimum of three clock after the falling edge

of either -ACK or BUSY. The counter is reset when-

ever the FIFO is reset. If write to parallel port operation

is attempted when the FIFO is full, the data will not be

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