ML145428_08 datasheet(7/14 Pages) LANSDALE

Nome de Peças	ML145428

Descrição Electrónicos	Asynchronous?뱓o?밪ynchronous

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Fabricante Electrônico	LANSDALE [LANSDALE Semiconductor Inc.]

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LANSDALE Semiconductor, Inc.

ML145428

When stripped data words reach the top of the Tx FIFO they

are loaded into the SYNCHRONOUS CHANNEL TRANS-

MITTER and are sent using a special zero insertion technique.

When stripped data is being transmitted, the synchronous data

transmitter will insert a binary 0 after any succession of five

continuous 1’s of data. Therefore, using this technique, no pat-

tern of (01111110) or (11111110) can occur while sending

data. This also allows the DSI to synchronize itself to the

incoming synchronous data word boundaries based on the data

alone.

The receive section of the DSI (synchronous channel receiv-

er) performs the reverse operation by removing a binary 0 that

follows five continuous 1’s in order to recover the transmitted

data. (note that a binary 1 which follows five continuous 1’s is

not removed so that flags and breaks may be detected.) Figure

2B shows an example of this process.

If the incoming data rate at TxD exceeds the rate at which it

is output at DCO, the FIFO will fill. The TxS pin will go low

when the FIFO contains two or more words. TxS may, there-

fore, be used as a local Clear-to-Send control line at the asyn-

chronous interface port to avoid transmit data over-runs.

In order to insure synchronization during the transfer of a

continuous stream of data the DSI’s synchronous channel

transmitter will insert a flag synchronnizing word (01111110)

every 61st data word. The DSI’s synchronous channel receiver

checks for this synchronizing word and if not present, the loss

of synchronizaion will be indicated by the RxS pin being

latched low until the flag synchronizing word is received. Note

that under these conditions the data will continue to output at

RxD.

RECEIVE CIRCUIT

Data incoming from the synchronous channel is loaded into

the ML145428 at the DCI pin under the control of the DC and

DIE pins (see SYNCHRONOUS CHANNEL INTERFACE

section). Framing information, break code detection, and data

word recovery functions are performed by the SYNCHRO-

NOUS CHANNEL RECEIVER. Recovered data words are

loaded into the four word deep Rx FIFO. When the recovered

data words reach the top of the Rx FIFO they are taken by the

DATA FORMATTER, start and stop bits are re-inserted and

the re-constructed asynchronous data is output at the TxD pin

at the same baud rate as the transmit side. The number of stop

bits and word length are those selected by the SB and DL pins.

Loss of framing, if it occurs, is indicated by the RxS pin

going low. Data will continue to be output under these condi-

tions, but RxS will remain low until frame synchronization,

i.e., the detection of a framing flag word, is re-established. If

the output data rate is less than the data rate of the incoming

synchronous data channel, data will be lost at the rate of one

word at a time due to the bottom word on the Rx FIFO being

overwritten. In order to prevent data loss (in the form of asyn-

chronous terminal to asynchronous terminal over-runs) due to

clock slip between remote DSI links, (during long bursts the

stop bit which it re-creates at its RxD output by 1/32nd. This

action allows the originator of a transmission (of asynchronous

data) to be up to 3% faster than the receive device is expecting

for any given data rate. This tolerance is well with in the nor-

mally expected differences in clock frequencies between

remote stations. If the Rx FIFO is overwriting the RxS line

will pulse low for one DC clock period following the over-

writing of the bottom level of the Rx FIFO.

INITIALIZATION

Initialization is accomplished by use of the RESET pin.

When held low, the internal FIFOs are cleared, the TxD input

appears high to the data strippers, internal circuitry. DCO is

forced to a high impedance state, TxS and RxS are forced low.

When brought high normal operation resumes and and the syn-

chronous channel transmitter sends the flag code until data has

reached the top of the Tx FIFO. Note that the TxS line will

immediately go high after RESET goes high, while RxS will

remain low until framing is detected. The synchronous channel

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