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ADF4154BCP Folha de dados(PDF) 9 Page - Analog Devices

Nome de Peças ADF4154BCP
Descrição Electrónicos  Fractional-N Frequency Synthesizer
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Página de início  http://www.analog.com
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ADF4154BCP Folha de dados(HTML) 9 Page - Analog Devices

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ADF4154
Rev. 0 | Page 9 of 20
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that the REFIN pin is not loaded on
power-down.
BUFFER
TO R COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
Figure 17. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AVDD
2k
2k
RFINB
RFINA
Figure 18. RF Input Stage
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RFOUT) equation is
(
)
(
)
MOD
FRAC
INT
F
RF
PFD
OUT
+
×
=
(1)
where RFOUT is the output frequency of the external voltage
controlled oscillator (VCO).
(
) R
D
REF
F
IN
PFD
+
×
=
1
(2)
where:
REFIN
is the reference input frequency.
D
is the REFIN doubler bit.
R
is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT
is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD
is the preset modulus ratio of binary 12-bit program-
mable FRAC counter (2 to 4095).
FRAC
is the preset fractional ratio of binary 12-bit
programmable FRAC counter (0 to MOD).
RF R COUNTER
The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 15 are allowed.
THIRD ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N COUNTER
Figure 19. A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 20 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
U3
CLR2
Q2
D2
U2
DOWN
UP
HI
HI
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1
D1
U1
Figure 20. PFD Simplified Schematic


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