CY7C1541KV18 datasheet(23/27 Pages) CYPRESS

Nome de Peças	CY7C1541KV18

Descrição Electrónicos	72-Mbit QDR짰II SRAM 4-Word BurstArchitecture (2.0 Cycle Read Latency)

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Fabricante Electrônico	CYPRESS [Cypress Semiconductor]

Página de início	http://www.cypress.com

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CY7C1541KV18, CY7C1556KV18

CY7C1543KV18, CY7C1545KV18

Document Number: 001-15700 Rev. *F

Page 23 of 27

Switching Characteristics

Over the Operating Range [23, 24]

Cypress

Parameter

Consortium

Parameter

Description

450 MHz

400 MHz

375 MHz

333 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

tPOWER

VDD(Typical) to the First Access

[25]

111

1

ms

tCYC

tKHKH

K Clock Cycle Time

2.2

8.4

2.5

8.4

2.66

8.4

3.0

8.4

ns

tKH

tKHKL

Input Clock (K/K) HIGH

0.4–0.4

–0.4–0.4

–

ns

tKL

tKLKH

Input Clock (K/K) LOW

0.4–0.4

–0.4–0.4

–

ns

tKHKH

K Clock Rise to K Clock Rise

(rising edge to rising edge)

0.94

–1.06–

1.13–1.28

–

ns

Setup Times

tSA

tAVKH

Address Setup to K Clock Rise

0.275

–

0.4

–

0.4

–

0.4

–

ns

tSC

tIVKH

Control Setup to K Clock Rise (RPS, WPS)

0.275

–0.4

–0.4–0.4

–

ns

tSCDDR

tIVKH

DDR Control Setup to Clock (K/K) Rise

(BWS0, BWS1, BWS2, BWS3)

0.22

–0.28–

0.28–0.28

–

ns

tSD

tDVKH

D[X:0] Setup to Clock (K/K) Rise

0.22

–0.28–

0.28–0.28

–

ns

Hold Times

tHA

tKHAX

Address Hold after K Clock Rise

0.275

–0.4

–0.4–0.4

–

ns

tHC

tKHIX

Control Hold after K Clock Rise (RPS, WPS)

0.275

–0.4

–0.4–0.4

–

ns

tHCDDR

tKHIX

DDR Control Hold after Clock (K/K) Rise

(BWS0, BWS1, BWS2, BWS3)

0.22

–0.28–

0.28–0.28

–

ns

tHD

tKHDX

D[X:0] Hold after Clock (K/K) Rise

0.22

–0.28–

0.28–0.28

–

ns

Output Times

tCO

tCHQV

K/K Clock Rise to Data Valid

–

0.45–

0.45

–0.45–

0.45

ns

tDOH

tCHQX

Data Output Hold after Output K/K Clock Rise

(Active to Active)

–0.45

–

–0.45

–

–0.45

–

–0.45

–

ns

tCCQO

tCHCQV

K/K Clock Rise to Echo Clock Valid

–

0.45–

0.45

–0.45–

0.45

ns

tCQOH

tCHCQX

Echo Clock Hold after K/K Clock Rise

–0.45

–

–0.45

–

–0.45

–

–0.45

–

ns

tCQD

tCQHQV

Echo Clock High to Data Valid

0.15

0.20

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.15

–

–0.20

–

–0.20

–

–0.20

–

ns

tCQH

tCQHCQL

Output Clock (CQ/CQ) HIGH [26]

0.85

–

1.0

–

1.08

–

1.25

–

ns

tCQHCQH

CQ Clock Rise to CQ Clock Rise

(rising edge to rising edge)

[26]

0.85

–

1.0

–

1.08

–

1.25

–

ns

tCHZ

tCHQZ

Clock (K/K) Rise to High Z

(Active to High Z) [27, 28]

–

0.45–

0.45

–0.45–

0.45

ns

tCLZ

tCHQX1

Clock (K/K) Rise to Low Z [27, 28]

–0.45

–

–0.45

–

–0.45

–

–0.45

–

ns

tQVLD

tCQHQVLD

Echo Clock High to QVLD Valid [29]

–0.15 0.15 –0.20 0.20 –0.20 0.20 –0.20 0.20

ns

PLL Timing

tKC Var

Clock Phase Jitter

–

0.15

–

0.20

–

0.20

–

0.20

ns

tKC lock

PLL Lock Time (K)

20–20–20–20–

μs

tKC Reset

K Static to PLL Reset [30]

30

ns

Notes

24. When a part with a maximum frequency above 333 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being

operated and outputs data with the output timings of that frequency range.

25. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be

initiated.

26. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by

design and are not tested in production.

27. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms” on page 22. Transition is measured ± 100 mV from steady-state

voltage.

28. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

29. tQVLD spec is applicable for both rising and falling edges of QVLD signal.

30. Hold to >VIH or <VIL.

[+] Feedback

Nº de peça semelhante - CY7C1541KV18

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