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FM16W08-SGTR Folha de dados(PDF) 5 Page - Cypress Semiconductor |
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FM16W08-SGTR Folha de dados(HTML) 5 Page - Cypress Semiconductor |
5 / 18 page FM16W08 Document Number: 001-86210 Rev. *F Page 5 of 18 accessed data is located in different rows. Regardless, F-RAM offers substantially higher write endurance than other nonvolatile memories. The rated endurance limit of 1014 cycles will allow 150,000 accesses per second to the same row for over 20 years. F-RAM Design Considerations When designing with F-RAM for the first time, users of SRAM will recognize a few minor differences. First, bytewide F-RAM memories latch each address on the falling edge of chip enable. This allows the address bus to change after starting the memory access. Since every access latches the memory address on the falling edge of CE, users cannot ground it as they might with SRAM. Users who are modifying existing designs to use F-RAM should examine the memory controller for timing compatibility of address and control pins. Each memory access must be qualified with a LOW transition of CE. In many cases, this is the only change required. An example of the signal relationships is shown in Figure 2 below. Also shown is a common SRAM signal relationship that will not work for the FM16W08. The reason for CE to strobe for each address is twofold: it latches the new address and creates the necessary pre-charge period while CE is HIGH. A second design consideration relates to the level of VDD during operation. Battery-backed SRAMs are forced to monitor VDD in order to switch to battery backup. They typically block user access below a certain VDD level in order to prevent loading the battery with current demand from an active SRAM. The user can be abruptly cut off from access to the nonvolatile memory in a power down situation with no warning or indication. F-RAM memories do not need this system overhead. The memory will not block access at any VDD level that complies with the specified operating range. The user should take measures to prevent the processor from accessing memory when VDD is out-of-tolerance. The common design practice of holding a processor in reset during power-down may be sufficient. It is recommended that chip enable is pulled HIGH and allowed to track VDD during power-up and power-down cycles. It is the user’s responsibility to ensure that chip enable is HIGH to prevent accesses below VDD min. (2.7 V). Figure 3 shows a pull-up resistor on CE, which will keep the pin HIGH during power cycles, assuming the MCU / MPU pin tristates during the reset condition. The pull-up resistor value should be chosen to ensure the CE pin tracks VDD to a high enough value, so that the current drawn when CE is LOW is not an issue. Figure 2. Chip Enable and Memory Address Relationships Valid Strobing of CE F-RAM Signaling CE Address A1 A2 Data D1 D2 Invalid Strobing of CE SRAM Signaling CE Address A1 A2 Data D1 D2 Figure 3. Use of Pull-up Resistor on CE MCU / MPU CE WE OE A 12-0 DQ 7-0 FM16W08 VDD |
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