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ADF4218BRU Folha de dados(PDF) 10 Page - Analog Devices |
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ADF4218BRU Folha de dados(HTML) 10 Page - Analog Devices |
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10 / 20 page  REV. 0 ADF4216/ADF4217/ADF4218 –10– CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown below in Figure 2. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. BUFFER 100k SW2 NC NC SW1 REFIN SW3 NO TO R COUNTER POWER-DOWN CONTROL Figure 2. Reference Input Stage IF/RF INPUT STAGE The IF/RF input stage is shown in Figure 3. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. 2k RFINA AVDD BIAS GENERATOR 2k RFINB AGND Figure 3. IF/RF Input Stage PRESCALER The dual modulus prescaler (P/P+1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). This prescaler, operating at CML levels, takes the clock from the IF/RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. It is based on a synchronous 4/5 core. The prescaler is selectable. On the IF side it can be set to either 8/9 (DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set to 1). On the RF side it can be set to 64/65 (DB20 of the RF AB Counter Latch set to 0) or 32/33 (DB20 set to 1). See Tables IV and VI. A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feed- back counter. The devices are guaranteed to work when the prescaler output is 165 MHz or less. Typically they will work with 200 MHz output from the prescaler. Pulse Swallow Function The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: fVCO = [(P × B) + A] × fREFIN/R fVCO = Output frequency of external voltage controlled oscilla- tor (VCO). P = Preset modulus of dual modulus prescaler (8/9, 16/17, etc.). B = Preset Divide Ratio of binary 11-bit counter (1 to 2047). A = Preset Divide Ratio of binary 6-bit A counter (0 to 63). fREFIN = Output frequency of the external reference frequency oscillator. R = Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383). R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase fre- quency detector (PFD). Division ratios from 1 to 16,383 are allowed. N = BP+A PRESCALER P/P+1 MODULUS CONTROL LOAD LOAD 11-BIT B COUNTER 6-BIT A COUNTER N DIVIDER FROM IF/RF INPUT STAGE TO PFD Figure 4. A and B Counters PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. CHARGE PUMP U3 CP DELAY ELEMENT D1 Q1 U1 CLR1 UP HI IN D1 Q1 U1 CLR2 DOWN HI – IN Figure 5. PFD Simplified Schematic |
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