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ST2202 Folha de dados(PDF) 10 Page - List of Unclassifed Manufacturers

Nome de Peças ST2202
Descrição Electrónicos  8 BIT Integrated Microcontroller with 256K Bytes ROM
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Fabricante Electrônico  ETC [List of Unclassifed Manufacturers]
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Sitronix
ST2202
Ver 2.0a
10/65
2003-May-05
$040
LSSAL*
W
SSA[7]
SSA[6]
SSA[5]
SSA[4]
SSA[3]
SSA[2]
SSA[1]
SSA[0]
0000 0000
$041
LSSAH*
W
SSA[15]
SSA[14]
SSA[13]
SSA[12]
SSA[11]
SSA[10]
SSA[9]
SSA[8]
0000 0000
$042
LVPW*
W
VP[7]
VP[6]
VP[5]
VP[4]
VP[3]
VP[2]
VP[1]
VP[0]
0000 0000
$043
LXMAX
R/W
XM[7]
XM[6]
XM[5]
XM[4]
XM[3]
XM[2]
XM[1]
XM[0]
0000 0000
$044
LYMAX
R/W
YM[7]
YM[6]
YM[5]
YM[4]
YM[3]
YM[2]
YM[1]
YM[0]
0000 0000
$045
LPAN
R/W
-
-
-
-
-
PAN[2]
PAN[1]
PAN[0]
- - - - -000
$047
LCTR
R/W
LPWR
BLNK
REV
-
-
-
-
-
100- - - - -
$048
LCKR*
W
-
-
-
LMOD
LCK[3]
LCK[2]
LCK[1]
LCK[0]
- - -0 0000
$049
LFRA*
W
-
-
FRA[5]
FRA[4]
FRA[3]
FRA[2]
FRA[1]
FRA[0]
- - 00 0000
$04A
LAC
R/W
-
-
-
AC[4]
AC[3]
AC[2]
AC[1]
AC[0]
- - -0 0000
$04B
LPWM
R/W
-
-
LPWM[5]
LPWM[4]
LPWM[3]
LPWM[2]
LPWM[1]
LPWM[0] - - 00 0000
$04C
PL*
R/W
PL[7]
PL[6]
PL[5]
PL[4]
PL[3]
PL[2]
PL[1]
PL[0]
1111 1111
$04E
PCL*
W
PCL[7]
PCL[6]
PCL[5]
PCL[4]
PCL[3]
PCL[2]
PCL[1]
PCL[0]
0000 0000
$050
SDAT0AL
R/W
SD[7]
SD[6]
SD[5]
SD[4]
SD[3]
SD[2]
SD[1]
SD[0]
???? ????
$051
SDATAH
R/W
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
???? ????
$052
SCTR
R/W
SPIEN
RXIEN
ERIEN
MEREN
DRINV
POL
PHA
SMOD
0000 0000
$053
SCKR
R/W
-
SCK[2]
SCK[1]
SCK[0]
BC[3]
BC[2]
BC[1]
BC[0]
-000 0000
R
-
RXRDY
TXEMP
SBZ
-
MDERR
OERR
BCERR
-000 -000
$054
SSR*
W
Write any value to clear SSR
$060
UCTR
R/W
-
-
-
-
PEN
PMOD
UMOD
BRK
- - - - 0000
R
-
FER
PER
OER
RXBZ
RXEN
TXBZ
TXEN
-000 0000
$061
USTR*
W
-
-
-
-
RXTRG
RXEN
TXTRG
TXEN
- - - - 0000
$062
IRCTR
R/W
RXINV
TXINV
-
-
-
PW1
PW0
IREN
00- - -000
$063
BCTR
R/W
TEST
-
-
-
-
BSTR
BMOD
BGREN
0- - - -000
$064
UDATA
R/W
UD[7]
UD[6]
UD[5]
UD[4]
UD[3]
UD[2]
UD[1]
UD[0]
???? ????
$066
BRS
R/W
BRS[7]
BRS[6]
BRS[5]
BRS[4]
BRS[3]
BRS[2]
BRS[1]
BRS[0]
???? ????
$067
BDIV
R/W
BDIV[7]
BDIV[6]
BDIV[5]
BDIV[4]
BDIV[3]
BDIV[2]
BDIV[1]
BDIV[0]
???? ????
Note: 1. Undefined bytes and bits should not be used.
* Do not use read-modify-write instructions, RMBx and SMBx, to write-only registers.
7.3 Bank Registers
There are four kinds of bank registers, interrupt bank register
(IRR), program ROM bank register (PRR), data ROM bank
register (DRR), and DMA source data bank register (DMR).
IRR, PRR refer to logic address range of $4000~$7FFF, while
DRR, DMR refer to the range of $8000~$FFFF. The register
length, addressable range, and size are listed in TABLE 7-2.
When normal process is running, address falls in one of the
two areas will activate either PRR or DRR.
In the case of interrupts, bit[11:8] of PRR will be masked to
zero and bit[7:0] will be replaced by IRR. This replacement
lasts until instruction RTI is met. That is, the interrupt vectors
and service routines will all base on IRR. Operation of IRR is
also enabled by IRREN of SYS.
Although a maximum number of 64M bytes can be addressed,
the physical size is lower than that because of the limit of chip
selects. Please refer to section 10 for more details.
TABLE 7-2 Bank Registers and Addressable Range
Address Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addressabl
e Range
Size
$031
IRR
R/W
IRR[7]
IRR[6]
IRR[5]
IRR[4]
IRR[3]
IRR[2]
IRR[1]
IRR[0]
$0000000~
$03FFFFF
4M
$032
PRRL
R/W
PRR[7]
PRR[6]
PRR[5]
PRR[4]
PRR[3]
PRR[2]
PRR[1]
PRR[0]
$033
PRRH R/W
-
-
-
-
PRR[11] PRR[10] PRR[9]
PRR[8]
$0000000~
$3FFFFFF
64M*
$034
DRRL
R/W DRR[7]
DRR[6]
DRR[5]
DRR[4]
DRR[3]
DRR[2]
DRR[1]
DRR[0]
$035
DRRH R/W
-
-
-
-
-
DRR[10] DRR[9]
DRR[8]
$0000000~
$3FFFFFF
64M*
$036
DMRL R/W DMR[7] DMR[6] DMR[5] DMR[4] DMR[3] DMR[2] DMR[1] DMR[0]
$037
DMRH R/W
-
-
-
-
-
DMR[10] DMR[9] DMR[8]
$0000000~
$3FFFFFF
64M*
Note: * Please refer to section 10 for the limit of addressable size.
TABLE 7-3 System Control Register SYS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R
XSEL
OSTP
XSTP
XBAK
WSKP
WAIT
IRREN
HIGH
0000 0001
$030
SYS
W
XSEL
OSTP
XSTP
XBAK
WSKP
WAIT
IRREN
LVDEN
0000 0000
Bit 1: IRREN : Enable/Disable Bank register IRR
0 = Disable IRR
1 = Enable IRR


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