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CDCV857BGQLR Folha de dados(PDF) 6 Page - Texas Instruments

Nome de Peças CDCV857BGQLR
Descrição Electrónicos  2.5-V PHASE-LOCK LOOP CLOCK DRIVER
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

CDCV857BGQLR Folha de dados(HTML) 6 Page - Texas Instruments

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CDCV857B, CDCV857BI
2.5V PHASELOCK LOOP CLOCK DRIVER
SCAS689 − FEBRUARY 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
Without load
fO = 170 MHz
100
110
Without load
fO = 200 MHz
105
120
Differential outputs
terminated with
fO = 170 MHz
200
240
IDD
Dynamic current on VDDQ
terminated with
120
Ω/CL = 0 pF
fO = 200 MHz
210
250
mA
Differential outputs
terminated with
fO = 170 MHz
260
300
terminated with
120
Ω/CL = 14 pF
fO = 200 MHz
280
320
∆C
Part-to-part input capacitance
variation
VDDQ = 2.5 V, VI = VDDQ or GND
1
pF
CI(∆)
Input capacitance difference between
CLK and CLKB, FBIN, and FBINB
VDDQ = 2.5 V, VI = VDDQ or GND
0.25
pF
CO
Output capacitance
VDDQ = 2.5 V, VO = VDDQ or GND
2.5
3
3.5
pF
† All typical values are at a respective nominal VDDQ.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fCLK
Operating clock frequency
60
200
MHz
fCLK
Application clock frequency
60
200
MHz
Input clock duty cycle
40%
60%
Stabilization time{ (PLL mode)
10
µs
Stabilization time} (Bypass mode)
30
ns
† The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply
for input modulation under SSC application.
‡ A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
switching characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLHw
Low to high level propagation delay time
Test mode/CLK to any output
3.5
ns
tPHLw
High-to low level propagation delay time
Test mode/CLK to any output
3.5
ns
tjit(per)W
Jitter (period), See Figure 7
66 MHz
−60
60
ps
tjit(per)W
Jitter (period), See Figure 7
100/133/167/200 MHz
−35
35
ps
tjit(cc)W
Jitter (cycle-to-cycle), See Figure 4
66 MHz
−75
75
ps
tjit(cc)W
Jitter (cycle-to-cycle), See Figure 4
100/133/167/200 MHz
−50
50
ps
tjit(hper)W
Half-period jitter, See Figure 8
66 MHz
−100
100
ps
tjit(hper)W
Half-period jitter, See Figure 8
100/133/167/200 MHz
−75
75
ps
tslr(o)
Output clock slew rate, See Figure 9
Load: 120
Ω/14 pF
1
2
V/ns
t(Ø)
Static phase offset, See Figure 5
66 MHz
–100
100
ps
t(Ø)
Static phase offset, See Figure 5
100/133/167/200 MHz
–50
50
ps
tsk(o)
Output skew, See Figure 6
Load: 120
Ω/14 pF
70
100
ps
tr, tf
Output rise and fall times (20% − 80%)
Load: 120
Ω/14 pF
600
900
ps
§ Refers to the transition of the noninverting output.
¶ This parameter is assured by design but can not be 100% production tested.


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