CDCV857BIDGGR datasheet(4/14 Pages) TI

Nome de Peças	CDCV857BIDGGR

Descrição Electrónicos	2.5-V PHASE-LOCK LOOP CLOCK DRIVER

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Fabricante Electrônico	TI [Texas Instruments]

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CDCV857B, CDCV857BI

2.5V PHASELOCK LOOP CLOCK DRIVER

SCAS689 − FEBRUARY 2003

4

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

DESCRIPTION

NAME

DGG

GQL

DESCRIPTION

AGND

17

H1

Ground for 2.5

-V analog supply

AVDD

16

G2

2.5

-V Analog supply

CLK, CLK

13, 14

F1, F2

I

Differential clock input

FBIN, FBIN

35, 36

F5, F6

I

Feedback differential clock input

FBOUT, FBOUT

32, 33

H6, G5

O

Feedback differential clock output

GND

1, 7, 8, 18,

24, 25, 31,

41, 42, 48

A3, A4,

C1, C2,

C5, C6,

H2, H5,

K3, K4

Ground

PWRDWN

37

E6

I

Output enable for Y and Y

VDDQ

4, 11, 12,

15, 21, 28,

34, 38, 45

B3, B4,

E1, E2,

E5, G1,

G6, J3, J4

2.5-V Supply

Y[0:9]

3, 5, 10,

20, 22, 27,

29, 39, 44,

46

A1, B2,

D1, J2,

K1, A6,

B5, D6,

J5, K6

O

Buffered output copies of input clock, CLK

Y[0:9]

2, 6, 9, 19,

23, 26, 30,

40, 43, 47

A2, B1,

D2, J1,

K2, A5,

B6, D5,

J6, K5

O

Buffered output copies of input clock, CLK

absolute maximum ratings over operating free-air temperature (unless otherwise noted)†

Supply voltage range, VDDQ, AVDD

0.5 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Notes 1 and 2)

–

0.5 V to VDDQ + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Notes 1 and 2)

–

0.5 V to VDDQ + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VDDQ)

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VDDQ)

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VDDQ)

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current to GND or VDDQ

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

θJA (see Note 3): GQL package

137.6

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range Tstg

–

65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

2. This value is limited to 3.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

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