AUIRS1170S

25

Rev. 2.3

2016-09-03

Suggested pcb layout and footprint

The exposed pad on the bottom side of the package has been introduced to improve the power dissipation

capability of the device. It is weakly electrically connected to the IC substrate, which is at Vs potential.

Therefore, special care has to be taken when designing the board layout.

Figure 20 below show two possible footprints. In both cases, the pad has no pcb traces to any signal. It may be

connected to Vs (pin6), if needed for layout simplification.

Both layout examples use DirectFet™ as synch.rectification devices; as also reported in AN1205, it is important to

have gate connections very similar to each other when several mosfets in parallel are used to carry high currents.

To avoid different Tdon and Tdoff delays due to gate traces inductance.

In the bottom example, the gate connections are optimized from the above point of view.

Figure 20: suggested footprints