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AD8324JRQ-REEL Folha de dados(PDF) 4 Page - Analog Devices

Nome de Peças AD8324JRQ-REEL
Descrição Electrónicos  3.3 V Upstream Cable Line Driver
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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AD8324JRQ-REEL Folha de dados(HTML) 4 Page - Analog Devices

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AD8324
Rev. 0 | Page 4 of 16
1 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz.
2 Guaranteed by design and characterization to ±6 sigma for TA = 25°C.
3 Guaranteed by design and characterization to ±3 sigma for TA = 25°C.
4 Measured through a 1:1 transformer.
5 Specification is worst case over all gain codes.
6 VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
Table 2. DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 3.3 V, unless otherwise noted
Parameter
Min
Typ
Max
Unit
Logic 1 Voltage
2.1
3.3
V
Logic 0 Voltage
0
0.8
V
Logic 1 Current (VINH = 3.3 V), CLK, SDATA, DATEN
0
20
nA
Logic 0 Current (VINL = 0 V), CLK, SDATA, DATEN
−600
−100
nA
Logic 1 Current (VINH = 3.3 V), TXEN
50
190
µA
Logic 0 Current (VINL = 0 V), TXEN
−250
−30
µA
Logic 1 Current (VINH = 3.3 V), SLEEP
50
190
µA
Logic 0 Current (VINL = 0 V), SLEEP
−250
−30
µA
TIMING REQUIREMENTS
Table 3. VCC = 3.3 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted
Parameter
Min
Typ
Max
Unit
Clock Pulse Width (tWH)
16.0
ns
Clock Period (tC)
32.0
ns
Setup Time SDATA vs. Clock (tDS)
5.0
ns
Setup Time DATEN vs. Clock (tES)
15.0
ns
Hold Time SDATA vs. Clock (tDH)
5.0
ns
Hold Time DATEN vs. Clock (tEH)
3.0
ns
Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)
10
ns
tDS
CLK
VALID DATA WORD G1
MSB . . . LSB
SDATA
DATEN
TXEN
ANALOG
OUTPUT
VALID DATA WORD G2
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
SIGNAL AMPLITUDE (p-p)
tC
tVUH
tES
tEH
tOFF
tGS
tCN
Figure 3. Serial Interface Timing
CLK
SDATA
MSB
MSB-1
MSB-2
VALID DATA BIT
tDS
tDH
Figure 4. SDATA Timng


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