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74HC3G07 Folha de dados(PDF) 2 Page - NXP Semiconductors |
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74HC3G07 Folha de dados(HTML) 2 Page - NXP Semiconductors |
2 / 14 page 2003 Oct 15 2 Philips Semiconductors Product specification Buffer with open-drain outputs 74HC3G07; 74HCT3G07 FEATURES • Wide supply voltage range from 2.0 to 6.0 V • High noise immunity • Low power dissipation • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Multiple package options • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74HC3G/HCT3G07 is a high-speed Si-gate CMOS device. Specified in compliance with JEDEC standard no. 7A. The 74HC3G/HCT3G07 provides three non-inverting buffers. The outputs of the 74HC3G/HCT3G07 devices are open drains and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For digital operation this device must have a pull-up resistor to establish a logic HIGH-level. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 6.0 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑ (CL × VCC2 × fo) = sum of outputs. 2. For 74HC3G07 the condition is VI = GND to VCC. For 74HCT3G07 the condition is VI = GND to VCC − 1.5 V. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC3G HCT3G tPZL propagation delay nA to nY CL = 50 pF; VCC = 4.5 V 9 11 ns tPLZ propagation delay nA to nY CL = 50 pF; VCC = 4.5 V 1110ns CI input capacitance 1.5 1.5 pF CPD power dissipation capacitance notes 1 and 2 4 4 pF |
Nº de peça semelhante - 74HC3G07 |
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Descrição semelhante - 74HC3G07 |
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