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AD805 Folha de dados(PDF) 11 Page - Analog Devices |
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AD805 Folha de dados(HTML) 11 Page - Analog Devices |
11 / 12 page AD805 –11– REV. 0 LARGE FACTOR FREQUENCY MULTIPLICATION — TO 155.52 MHZ The AD805-VCXO combination can be used to multiply a frequency at the AD805’s DATAIN by a large integer multiple. This is useful for generating a 155.52 MHz bit clock from a 19.44 MHz byte clock (multiplication factor of 8). The highly accurate center frequency of the VCXO makes even larger factor frequency multiplication possible. The VCXO will not lock on a false harmonic even for large multiplication factors. For example, a VCXO with center frequency accuracy of 100 ppm will allow frequency multiplication by a factor as large as 5000. This is because the 5000th harmonic of 31.104 kHz is 155.52 MHz, and the 4999th and the 5001st harmonics are 200 ppm away from the VCXO center frequency. Since the accuracy and tuning range of the VCXO constrain its output frequency to within 100 ppm of center frequency, the circuit will reliably pick the 5000th harmonic. Frequency multiplication by an odd factor is possible using the AD805-VCXO combination. This is not obvious. Consider a 51.84 MHz input multiplied by a factor of 3 to get to 155.52 MHz. In this case, the edge spacing of the 51.84 MHz signal is 9.65 ns, or 1-1/2 periods of the expected 155.52 MHz output. In theory, every other edge of the 51.84 MHz at the AD805’s DATAIN is interpreted as 180 ° out of phase. In practice, however, the inherent loop jitter dithers these edges to give +179 ° then –179° out of phase measurements on alternate edges. Measurements on these alternate edges cancel. The circuit phase locks to the other set of alternate edges. The very low gain of the VCXO and the narrow bandwidth of the jitter transfer function gives an output that has low jitter even though alternate input edges are out of phase. When multiplying by a factor of 3, the DATAOUT will have a repeating 110 or 100 pattern. Either pattern can occur since either the rising or falling edges of the 51.84 MHz signal at the DATAIN can be the out of phase set of alternate edges. Figure 18 shows the output jitter performance of an AD805- VCXO circuit for different integer frequency multiplication factors. 60 0 10 100 INPUT CLOCK FREQUENCY – MHz 50 40 30 20 10 Figure 19. AD805-VCXO Circuit Clock Output Jitter vs. Integer Multiplier DESKEWING ISOCHRONOUS 155.52 MBPS DATA STREAMS The AD805 can be used for deskewing a 155.52 Mbps data stream to a reference 155.52 MHz clock when the clock is isochronous with the data. Figure 19 shows a diagram of an AD805 in a deskewing application. The data input to the AD802-155 clock recovery circuit and the data input to the AD805 were generated using the same 155.52 MHz clock. The AD805 data retiming loop formed by the voltage-controlled phase shifter, the phase detector, and the loop filter act to align the phase of the input data to the phase of the recovered clock. This eliminates skew that can exist between two isochronous data paths. The AD805 will track ±180° change in skew after initial locking without bit errors. If the skew changes by more than ±180° after lock, it is possible to exceed the range of the voltage controlled phase shifter. Exceeding the phase shifter range will force the AD805 data retiming loop to reacquire to the center of the phase shifter. During this reacquisition, it is possible to make 3000 bit errors. PHASE DETECTOR RECOVERED CLOCK COMPENSATING ZERO C D VCO RETIMING MODULE FRAC OUTPUT AD802-155 VOLTAGE CONTROLLED PHASE SHIFTER BUFFERED CLOCK AD805 GAIN REFERENCE DATA INPUT DATA INPUT VCXO CONTROL OUTPUT ∑ FREQUENCY DETECTOR RETIMING MODULE LOOP FILTER RETIMED DATA PHASE DETECTOR LOOP FILTER RETIMED DATA Figure 19. AD805 Deskewing Circuit Diagram OBSOLETE |
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