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74LVC2G132DCURE4 Folha de dados(PDF) 2 Page - Texas Instruments

Nome de Peças 74LVC2G132DCURE4
Descrição Electrónicos  DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
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74LVC2G132DCURE4 Folha de dados(HTML) 2 Page - Texas Instruments

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
1A
1B
1Y
2A
2B
2Y
7
3
1
2
5
6
Absolute Maximum Ratings
(1)
SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES547A – FEBRUARY 2004 – REVISED JUNE 2005
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(EACH GATE)
INPUTS
OUTPUT
Y
A
B
L
L
H
L
H
H
H
L
H
H
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range(2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state(2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
DCT package
220
θ
JA
Package thermal impedance(4)
DCU package
227
°C/W
YEP/YZP package
102
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of VCC is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7
2


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