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KMM366S1623CTY-GL Folha de dados(PDF) 2 Page - Samsung semiconductor |
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KMM366S1623CTY-GL Folha de dados(HTML) 2 Page - Samsung semiconductor |
2 / 11 page PC100 SDRAM MODULE KMM366S1623CTY REV. 0 August 1998 Preliminary PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. WP Write protection WP pin is connected to VSS through 47K Ω Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. |
Nº de peça semelhante - KMM366S1623CTY-GL |
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Descrição semelhante - KMM366S1623CTY-GL |
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