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DAC8814ICDBR Folha de dados(PDF) 3 Page - Texas Instruments |
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DAC8814ICDBR Folha de dados(HTML) 3 Page - Texas Instruments |
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3 / 31 page  www.ti.com ELECTRICAL CHARACTERISTICS (1) DAC8814 SBAS338 – JANUARY 2005 V DD = 2.7 V to 5.0 V ±10%; VSS = 0 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless otherwise noted. DAC8814 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE(2) Resolution 16 Bits Relative accuracy INL DAC8814B ±4 LSB INL DAC8814C ±1 LSB Differential nonlinearity DNL DAC8814B ±1.5 LSB DNL DAC8814C ±1 LSB Output leakage current IOUTX Data = 0000h, TA = 25°C 10 nA IOUTX Data = 0000h, TA = TA max 20 nA Full-scale gain error GFSE Data = FFFFh ±0.75 ±3 mV Full-scale tempco(3) TCVFS 1 ppm/ °C Feedback resistor RFBX VDD = 5 V 5 k Ω REFERENCE INPUT VREFX Range VREFX -15 15 V Input resistance RREFX 4 6 8 k Ω Input resistance match RREFX Channel-to-channel 1 % Input capacitance(3) CREFX 5 pF ANALOG OUTPUT Output current IOUTX Data = FFFFh 1.25 2.5 mA Output capacitance(3) COUTX Code-dependent 80 pF LOGIC INPUTS AND OUTPUT Input low voltage VIL VDD = +2.7 V 0.6 V VIL VDD = +5 V 0.8 V Input high voltage VIH VDD = +2.7 V 2.1 V VIH VDD = +5 V 2.4 V Input leakage current IIL 1 µA Input capacitance(3) CIL 10 pF Logic output low voltage VOL IOL = 1.6 mA 0.4 V Logic output high voltage VOH IOH = 100 µA 4 V INTERFACE TIMING(3), (4) Clock width high tCH 25 ns Clock width low tCL 25 ns CS to Clock setup tCSS 0 ns Clock to CS hold tCSH 25 ns Clock to SDO prop delay tPD 2 20 ns Load DAC pulsewidth tLDAC 25 ns Data setup tDS 20 ns Data hold tDH 20 ns Load setup tLDS 5 ns Load hold tLDH 25 ns (1) Specifications subject to change without notice. (2) All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter amplifier. The DAC8814 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at +25°C. (3) These parameters are specified by design and not subject to production testing. (4) All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 3 |
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