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TL16C550DIRHB Folha de dados(PDF) 10 Page - Texas Instruments

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Nome de Peças TL16C550DIRHB
Descrição Electrónicos  ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
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TL16C550DIRHB Folha de dados(HTML) 10 Page - Texas Instruments

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TL16C550D, TL16C550DI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS597C − APRIL 2004 − REVISED JUNE 2005
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (for RHB package)
TERMINAL
NAME
NUMBER
I/O
DESCRIPTION
A0
A1
A2
19
18
17
I
Register select. A0 − A2 are used during read and write operations to select the ACE register to read from or
write to. See Table 1 for register addresses, and see the ADS description.
CS2
8
I
Chip select. When CS2 is low, the ACE is selected. When CS2 is high, the ACE remains inactive.
CTS
24
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (
∆CTS) of the modem status register indicates that CTS has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels
and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to
control the transmitter.
D0
D1
D2
D3
D4
D5
D6
D7
29
30
31
32
1
3
4
5
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.
DCD
26
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (
∆DCD) of the modem status register indicates that DCD has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when DCD
changes levels, an interrupt is generated.
DSR
25
I
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the
modem status register. Bit 1 (
∆DSR) of the modem status register indicates DSR has changed levels since
the last read from the modem status register. If the modem status interrupt is enabled when DSR changes
levels, an interrupt is generated.
DTR
22
O
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR
is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the
DTR bit.
INTRPT
20
O
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed
out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT
is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.
MR
23
I
Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals
(see Table 2).
NC
2, 9,
15, 16
No connection
RD1
14
I
Read input. When RD1 is active (low) while the ACE is selected, the CPU is allowed to read status information
or data from a selected ACE register.
RI
27
I
Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem
status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high
level since the last read from the modem status register. If the modem status interrupt is enabled when this
transition occurs, an interrupt is generated.
RTS
21
O
Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS
is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the
auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic.


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