FM25L04

Rev. 2.0

May 2005

Page 2 of 12

Instruction Decode

Clock Generator

Control Logic

Write Protect

Instruction Register

Address Register

Counter

`

128 x 32

FRAM Array

9

Data I/O Register

8

Nonvolatile Status

Register

3

WP

CS

HOLD

SCK

SO

SI

Figure 1. Block Diagram

Pin Descriptions

Pin Name

I/O

Description

/CS

Input

Chip Select: This active low input activates the device. When high, the device enters

low-power standby mode, ignores other inputs, and all outputs are tri-stated. When

low, the device internally activates the SCK signal. A falling edge on /CS must occur

prior to every op-code.

SCK

Input

Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on

the rising edge and outputs occur on the falling edge. Since the device is static, the

clock frequency may be any value between 0 and 14 MHz and may be interrupted at

any time.

/HOLD

Input

Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation

for another task. When /HOLD is low, the current operation is suspended. The device

ignores any transition on SCK or /CS. All transitions on /HOLD must occur while

SCK is low.

/WP

Input

Write Protect: This active low pin prevents write operations to the memory array or

the status register. A complete explanation of write protection is provided below.

SI

Input

Serial Input: All data is input to the device on this pin. The pin is sampled on the

rising edge of SCK and is ignored at other times. It should always be driven to a valid

logic level to meet IDD specifications.

* SI may be connected to SO for a single pin data interface.

SO

Output

Serial Output: This is the data output pin. It is driven during a read and remains tri-

stated at all other times including when /HOLD is low. Data transitions are driven on

the falling edge of the serial clock.

* SO may be connected to SI for a single pin data interface.

VDD

Supply

Power Supply (2.7V to 3.6V)

VSS

Supply

Ground