Preliminary Rev. 0.46 5/01
Copyright © 2001 by Silicon Laboratories
Si5022/23-DS046
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Si5022/Si5023
MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP
Features
High Speed Clock and Data Recovery device with Integrated Limiting Amp:
Applications
Description
The Si5022/23 is a fully integrated, high performance limiting amp and clock and
data recovery (CDR) IC for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or
Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided
for OC-48/STM-16 applications that employ forward error correction (FEC). An
external reference clock is not required; applications with or without an external
reference clock are supported. Silicon Laboratories’ DSPLL™ technology
eliminates sensitive noise entry points thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
The Si5022/23 represents a new standard in low jitter, low power, small size, and
integration for high speed LA/CDRs. It operates from either a 3.3 V (Si5023) or
2.5 V (Si5022) supply over the industrial temperature range (–40°C to 85°C).
Functional Block Diagram
! Supports OC-48/12/3, STM-16/4/1,
Gigabit Ethernet, and 2.7 Gbps FEC
! DSPLL™ Technology
! Low Power—370 mW (TYP)
! Small Footprint: 5 mm x 5 mm
! Bit-Error-Rate Alarm
! External Reference Not Required
!
Jitter Generation 3.0 mUIRMS(TYP)
! Loss-of-signal Level Alarm
! Data Slicing Level Control
! 10 mVPP Differential Sensitivity
! 2.5 V (Si5022) or 3.3 V (Si5023) Supply
! SONET/SDH/ATM Routers
! Add/Drop Multiplexers
! Digital Cross Connects
! Gigabit Ethernet Interfaces
! SONET/SDH Test Equipment
! Optical Transceiver Modules
! SONET/SDH Regenerators
! Board Level Serial Links
Lim iting
AM P
D SPL L TM
Phase-Locked
Loop
BU F
BU F
Retim er
DIN+
DIN–
LO S _ L V L
SL IC E_ L V L
LO S
2
2
2
LO L
CL K O UT+
CL K O UT–
DO UT+
DO UT–
CL K D S B L
Bias G en
R EXT
Squelch
C ontrol
DS Q L C H
R ESET /C AL
BE R _ AL M
RATS E L [1 :0 ]
2
R E FC LK+
R E FC LK–
(Optional)
LTR
BE R _ L V L
C ontrol
Ordering Information:
See page 14.
Pin Assignments
Si5022/23
1
RATESEL0
GND
Pad
Top View
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
22
23
24
25
26
27
28
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT–
TDI
P REL I MINARY D AT A S HEET
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