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AD5380EB Folha de dados(PDF) 8 Page - Analog Devices

Nome de Peças AD5380EB
Descrição Electrónicos  40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
–8–
AD5380
F SCL
400
kHz max
SCL Clock Frequency
t1
2.5
µs min
SCL Cycle Time
t2
0.6
µs min
tHIGH, SCL High Time
t3
1.3
µs min
tLOW, SCL Low Time
t4
0.6
µs min
tHD,STA, Start/Repeated Start Condition Hold Time
t5
100
ns min
tSU,DAT, Data Setup Time
t6
3
0.9
µs max
tHD,DAT, Data Hold Time
0
µs min
tHD,DAT, Data Hold Time
t7
0.6
µs min
tSU,STA, Setup Time for Repeated Start
t8
0.6
µs min
tSU,STO, Stop Condition Setup Time
t9
1.3
µs min
tBUF, Bus Free Time Between a STOP and a START Condition
t10
300
ns max
tR, Rise Time of SCL and SDA when Receiving
0
ns min
tR, Rise Time of SCL and SDA when Receiving (CMOS-Com
patible)
t11
300
ns max
tF, Fall Time of SDA when Transmitting
0
ns min
tF, Fall Time of SDA when Receiving (CMOS-Compatible)
300
ns max
tF, Fall Time of SCL and SDA when Receiving
20 + 0.1Cb
4
ns min
tF, Fall Time of SCL and SDA when Transmitting
C B
400
pF max
Capacitive Load for Each Bus Line
TIMING CHARACTERISTICS
(DVDD= 2.7V to 5.5V ; AVDD=+4.5V to +5.5V or +2.7V to +3.6V; AGND= DGND = 0 V; )
All specifications TMIN to TMAX unless otherwise noted.)
I2C SERIAL INTERFACE
Parameter
1,2
Limit at TMIN, TMAX
Units
Description
NOTES
1Guaranteed by design and characterization, not production tested.
2See Figure 5
3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH MIN of the SCL signal) in order to bridge the
undefined region of SCL’s falling edge.
4Cb is the total capacitance of one bus line in pF. t
R and tF measured between 0.3 VDD and 0.7 VDD.
SCL
SDA
START
CONDITION
t9
t3
t4
t6
t2
t5
t7
t8
t1
t4
t11
t10
REPEATED
START
CONDITION
STOP
CONDITION
Figure 5. I2C Compatible Serial Interface Timing Diagram


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