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ADE7756BN Folha de dados(PDF) 5 Page - Analog Devices

Nome de Peças ADE7756BN
Descrição Electrónicos  Active Energy Metering IC with Serial Interface
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADE7756BN Folha de dados(HTML) 5 Page - Analog Devices

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ADE7756
–5–
TIMING CHARACTERISTICS1, 2
Parameter
A, B Versions
Unit
Test Conditions/Comments
Write Timing
t1
20
ns (min)
CS falling edge to first SCLK falling edge.
t2
150
ns (min)
SCLK logic high pulsewidth.
t3
150
ns (min)
SCLK logic low pulsewidth.
t4
10
ns (min)
Valid Data Setup time before falling edge of SCLK.
t5
5
ns (min)
Data Hold time after SCLK falling edge.
t6
6.4
µs (min)
Minimum time between the end of data byte transfers.
t7
4
µs (min)
Minimum time between byte transfers during a serial write.
t8
100
ns (min)
CS Hold time after SCLK falling edge.
Read Timing
t9
4
µs (min)
Minimum time between read command (i.e., a write to Communication
Register) and data read.
t10
4
µs (min)
Minimum time between data byte transfers during a multibyte read.
t11
3
30
ns (min)
Data access time after SCLK rising edge following a write to the
Communications Register.
t12
4
100
ns (max)
Bus relinquish time after falling edge of SCLK.
10
ns (min)
t13
4
100
ns (max)
Bus relinquish time after rising edge of
CS.
10
ns (min)
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
2See timing diagram below and Serial Interface section of this data sheet.
3Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured
number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics
is the true bus relinquish time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200 A
1.6mA
IOL
CL
50pF
TO
OUTPUT
PIN
2.1V
IOH
Figure 1. Load Circuit for Timing Specifications
t5
t4
CS
SCLK
DIN
A4
A3
A2
A1
A0
DB7
MOST SIGNIFICANT BYTE
1
DB0
DB7
DB0
LEAST SIGNIFICANT BYTE
00
COMMAND BYTE
t1
t2
t3
t6
t7
t8
Figure 2. Serial Write Timing
CS
SCLK
DIN
A4
A3
A2
A1
A0
00
0
t1
t10
DOUT
DB7
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
COMMAND BYTE
DB0
DB7
DB0
t13
t12
t9
t11
t11
Figure 3. Serial Read Timing
(AVDD = DVDD = 5 V
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
XTAL, TMIN to TMAX = –40 C to +85 C, unless otherwise noted.)


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