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MC7455ARX933LF Folha de dados(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC7455ARX933LF Folha de dados(HTML) 4 Page - Freescale Semiconductor, Inc |
4 / 64 page MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1 4 Freescale Semiconductor Features – Thirty-two 64-bit FPRs for single- or double-precision operands — Four vector units and 32-entry vector register file (VRs) – Vector permute unit (VPU) – Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add instructions (vaddsbs, vaddshs, and vaddsws, for example) – Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for example) – Vector floating-point unit (VFPU) — Three-stage load/store unit (LSU) – Supports integer, floating-point, and vector instruction load/store traffic – Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations – Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle throughput – Four-cycle FPR load latency (single, double) with one-cycle throughput – No additional delay for misaligned access within double-word boundary – Dedicated adder calculates effective addresses (EAs) – Supports store gathering – Performs alignment, normalization, and precision conversion for floating-point data – Executes cache control and TLB instructions – Performs alignment, zero padding, and sign extension for integer data – Supports hits under misses (multiple outstanding misses) – Supports both big- and little-endian modes, including misaligned little-endian accesses • Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: — Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2 — A maximum of three instructions can be dispatched to the issue queues per clock cycle — Space must be available in the CQ for an instruction to dispatch (this includes instructions that are assigned a space in the CQ but not in an issue queue) • Rename buffers — 16 GPR rename buffers — 16 FPR rename buffers — 16 VR rename buffers • Dispatch unit — Decode/dispatch stage fully decodes each instruction • Completion unit — The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending. — Guarantees sequential programming model (precise exception model) — Monitors all dispatched instructions and retires them in order — Tracks unresolved branches and flushes instructions after a mispredicted branch |
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Descrição semelhante - MC7455ARX933LF |
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