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SN74AUP1G126 Folha de dados(PDF) 2 Page - Texas Instruments |
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SN74AUP1G126 Folha de dados(HTML) 2 Page - Texas Instruments |
2 / 17 page SN74AUP1G126 LOW POWER SINGLE BUS BUFFER GATE WITH 3STATE OUTPUT SCES596D – JULY 2004 – REVISED JUNE 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Tape and reel SN74AUP1G126YEPR _ _ _HN_ −40 °C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Tape and reel SN74AUP1G126YZPR _ _ _HN_ −40 °C to 85°C SOT (SOT-23) − DBV Tape and reel SN74AUP1G126DBVR H26_ SOT (SC-70) − DCK Tape and reel SN74AUP1G126DCKR HN_ SOT (SOT-553) − DRL Reel of 4000 SN74AUP1G126DRLR HN_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS OUTPUT OE A OUTPUT Y H H H H LL L X§ Z § Floating inputs allowed. logic diagram (positive logic) AY OE 1 24 |
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