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DM54LS323 Folha de dados(PDF) 4 Page - National Semiconductor (TI) |
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DM54LS323 Folha de dados(HTML) 4 Page - National Semiconductor (TI) |
4 / 8 page Functional Description The ’LS323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset shift left shift right parallel load and hold operations The type of operation is determined by S0 and S1 as shown in the Mode Select Table All flip-flop outputs are brought out through TRI-STATE buffers to separate IO pins that also serve as data inputs in the parallel load mode Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP All other state changes are also initiated by the LOW-to-HIGH CP transition Inputs can change when the clock is in either state provided only that the recommended setup and hold times relative to the rising edge of CP are observed A HIGH signal on either OE1orOE2 disables the TRI- STATE buffers and puts the IO pins in the high impedance state In this condition the shift load hold and reset opera- tions can still occur The TRI-STATE buffers are also dis- abled by HIGH signals on both S0 and S1 in preparation for a parallel load operation Mode Select Table Inputs Response SR S1 S0 CP LX X L Synchronous Reset Q0–Q7 e LOW HH H L Parallel Load IOnxQn HL H L Shift Right DS0xQ0 Q0xQ1 etc HHL L Shift Left DS7xQ7 Q7xQ6 etc H H H X Hold H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Logic Symbol TLF9829 – 2 VCC e Pin 20 GND e Pin 10 4 |
Nº de peça semelhante - DM54LS323 |
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Descrição semelhante - DM54LS323 |
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