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MC100EPT22DR2 Folha de dados(PDF) 1 Page - ON Semiconductor

Nome de Peças MC100EPT22DR2
Descrição Electrónicos  Dual LVTTL/LVCMOS to Differential LVPECL Translator
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
Página de início  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EPT22DR2 Folha de dados(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 2.0
1
Publication Order Number:
MC100EPT22/D
MC100EPT22
Dual LVTTL/LVCMOS to
Differential LVPECL Translator
The MC100EPT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Because LVPECL (Positive ECL) levels are used
only +3.3V and ground are required. The small outline 8–lead SOIC
package and the single gate of the EPT22 makes it ideal for those
applications where space, performance, and low power are at a
premium. Because the mature MOSAIC 5 process is used, low cost
and high speed can be added to the list of features.
420ps Typical Propagation Delay
Differential LVPECL Outputs
Small Outline SOIC Package
PNP LVTTL Inputs for Minimal Loading
Flow Through Pinouts
Q Output will default HIGH with inputs open
ESD Protection: 4.0 KV HBM, 200 V MM
Maximum Frequency > 1.1 GHz
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 164 devices
1
2
3
45
6
7
8
D0
GND
VCC
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
Q0
D1
Q1
Q1
Q0
LVPECL
LVTTL
ALYW
SO–8
D SUFFIX
CASE 751
PIN DESCRIPTION
PIN
Q0, Q1, Q0, Q1
D0, D1
LVTTL Inputs
FUNCTION
Diff. LVPECL Outputs
http://onsemi.com
VCC
Positive Supply
GND
Ground
MARKING DIAGRAM
Device
Package
Shipping
ORDERING INFORMATION
MC100EPT22D
SOIC
98 Units/Rail
MC100EPT22DR2
SOIC
2500 Tape & Reel
KPT22
1
8
1
8
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D


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