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AD7940BRM Folha de dados(PDF) 7 Page - Analog Devices |
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AD7940BRM Folha de dados(HTML) 7 Page - Analog Devices |
7 / 20 page AD7940 Rev. 0 | Page 7 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CS SDATA SCLK 6 5 4 VDD 1 GND 2 VIN 3 AD7940 TOP VIEW (Not to Scale) SOT-23 Figure 3. SOT-23 Pin Configuration NC = NO CONNECT AD7490 MSOP TOP VIEW (Not to Scale) VDD 1 GND 2 GND 3 VIN 4 CS SDATA NC SCLK 8 7 6 5 Figure 4. MSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. SOT-23 Pin No. MSOP Mnemonic Function 1 1 VDD Power Supply Input. The VDD range for the AD7940 is from 2.5 V to 5.5 V. 2 2, 3 GND Analog Ground. Ground reference point for all circuitry on the AD7940. All analog input signals should be referred to this GND voltage. 3 4 VIN Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. 4 5 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock input is also used as the clock source for the AD7940's conversion process. 5 7 SDATA Data Out. Logic output. The conversion result from the AD7940 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7940 consists of two leading zeros followed by 14 bits of conversion data that are provided MSB first. This will be followed by four trailing zeroes if CS is held low for a total of 24 SCLK cycles. See the Serial Interface section. 6 8 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7940 and framing the serial data transfer. N/A 6 NC No Connect. This pin should be left unconnected. |
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