MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

4–1

REV 1

7/95

1:5 Clock Distribution Chip

The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip

designed explicitly for low skew clock distribution applications. The

device can be driven by either a differential or single-ended ECL or, if

positive power supplies are used, PECL input signal. The LVEL14 is

functionally and pin compatible with the EL14 but is designed to operate

in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or

3.0V to 3.8V). If a single-ended input is to be used the VBB output should

be connected to the CLK input and bypassed to ground via a 0.01

µF

capacitor. The VBB output is designed to act as the switching reference

for the input of the LVEL14 under single-ended input conditions, as a

result this pin can only source/sink up to 0.5mA of current.

The LVEL14 features a multiplexed clock input to allow for the

distribution of a lower speed scan or test clock along with the high speed

system clock. When LOW (or left open and pulled LOW by the input

pulldown resistor) the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the outputs will only

be enabled/disabled when they are already in the LOW state. This avoids

any chance of generating a runt clock pulse when the device is

enabled/disabled as can happen with an asynchronous control. The

internal flip flop is clocked on the falling edge of the input clock, therefore

all associated specification limits are referenced to the negative edge of

the clock input.

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

Q1

Q2

Q3

Q4

17

18

16

15

14

13

12

4

3

5678

9

VCC

11

10

Q4

Q3

Q2

Q1

NC

SCLK

CLK

CLK

VBB

SEL

VEE

D

Q

1

0

Q0

19

20

2

1

VCC

Q0

EN

MC100LVEL14

MC100EL14

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

1

20

PIN

FUNCTION

CLK

Diff Clock Inputs

SCLK

Scan Clock Input

EN

Sync Enable

SEL

Clock Select Input

VBB

Reference Output

Q0–4

Diff Clock Outputs

PIN DESCRIPTION

CLK

L

H

X

X

X

SCLK

X

X

L

H

X

SEL

L

L

H

H

X

EN

L

L

L

L

H

Q

L

H

L

H

L*

FUNCTION TABLE

* On next negative transition of

CLK or SCLK