MC10SX1405

MOTOROLA

ECLinPS and ECLinPS Lite

DL140 — Rev 3

2

Figure 2. MC10SX1405 Simplified Block Diagram

MC10SX1405

OC3

OC12

Interface

RETIME

FF

PHASE–LOCKED

LOOP

2

2

2

DIV

8

REFCK

VARCK

PLLCK

RETIME

FF

RETCK

DI1:8

EPI

PARITY

CHECK

FCM

OOL

PERR

SOM

SOP

LASER

DRIVER

EO

CONTROL

SYSTEM

DIFFERENTIAL

TX OUTPUT

PARALLEL

DATA INPUT

MUX

SX1405 Theory of Operation

Operation of the SX1405 is straightforward. Parallel data

is input to the device. Serial–to–parallel conversion is

performed. Then the serial data is output at the selected line

rate clock. The 78 MByte/s or 19 MByte/s parallel data is

converted into a bit–serial 622 Mbit/s or 155 Mbit/s data

stream.

The on–chip PLL generates the 622 MHz or 155 MHz line

rate clock from a subrate clock. For testing and applications

which provide an external high–frequency bit clock, the

internal clock generation PLL may be bypassed.

SX1405 Block Diagram Functional Description

Phase Locked Loop

The on–chip Phase Locked Loop (PLL) synthesizes the

internal bit rate clock from the 19.44 / 38.66 / 77.78 MHz input

reference clock. The PLL consists of a phase / frequency

detector, loop filter, and Voltage Controlled Oscillator (VCO)

nominally operating at 1.2 GHz. Dividers provide the internal

clocks and a sub–rate clock output PLLCKP/PLLCKM

(differential PECL) for phase comparison.

REFCK/REFCKM is the differential input PLL reference

clock. The feedback, to close the loop of the PLL, is

VARCK/VARCKM, the differential input variable clock. Both

the REFCK and VARCK inputs can be driven by TTL levels if

the “minus” input (REFCKM and VARCKM) are left open.

An Out Of Lock indicator (OOL) is driven HIGH if the PLL

is not frequency locked with the input reference clock.

Parallel to Serial Conversion

In OC3 mode, converts a 4–bit (Nibble) 38.88 Mb/s or

8–bit (Byte) 19.44 Mb/s input to a differential 155.52 Mb/s

serial data output. In OC12 mode, converts an 8–bit 77.76

Mb/s input to a differential 622.08 Mb/s serial data output.

The input data is loaded into the Retime FF’s by the Retiming

Clock RETCK. Then the data is loaded into a shift register by

PLLCK. The data shifted out is ordered MSB (DI1) first and

LSB (DI8 or DI4) last.

Parity Check

The parity check provides a means of verifying the

integrity of the parallel to serial converter with minimal

overhead. The parity of the serial output data stream is

compared to the value of the Even Parity Input (EPI). If a

parity error is deteced, the Parity Error (PERR) output is set

HIGH. The PERR pin has an Open Collector TTL Output and

must be given a falling edge to reset the parity error detector.

SX1405 Control Signals

Reset (RSTN) – Used for testing and verification, the TTL

outputs are set to Tri–State and all divider flip–flops

and the parity generator are reset when RSTN = LOW.

This also sets PERR HIGH and PERR must be given a

falling edge to reset the parity error detector for normal

operation. An internal pull–up is provided on RSTN

allowing the device to operate normally if RSTN is not

used.

Low Speed Select (LSS) – Selects data rate. LOW = OC–12

(622.08 Mb/s), HIGH = OC–3 (155.52 Mb/s). An