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CAT24AC128JI-TE13 Folha de dados(PDF) 5 Page - Catalyst Semiconductor |
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CAT24AC128JI-TE13 Folha de dados(HTML) 5 Page - Catalyst Semiconductor |
5 / 11 page CAT24AC128 5 Doc. No. 1028, Rev. I 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device the master is accessing. Up to eight CAT24AC128 devices may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24AC128 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24AC128 then performs a Read or Write operation depending on the state of the R/ W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24AC128 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. Figure 4. Acknowledge Timing Figure 5. Slave Address Bits When the CAT24AC128 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24AC128 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24AC128. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24AC128 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24AC128 writes up to 64 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed A2 A1 A0 *A0, A1 and A2 must compare to its corresonding hard wired inputs (pins 1, 2 and 3). ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER |
Nº de peça semelhante - CAT24AC128JI-TE13 |
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Descrição semelhante - CAT24AC128JI-TE13 |
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