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LFEC40E-3F484C Folha de dados(PDF) 10 Page - Lattice Semiconductor

Nome de Peças LFEC40E-3F484C
Descrição Electrónicos  LatticeECP/EC Family Data Sheet
Download  117 Pages
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Fabricante Electrônico  LATTICE [Lattice Semiconductor]
Página de início  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFEC40E-3F484C Folha de dados(HTML) 10 Page - Lattice Semiconductor

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Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Routing
There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered allowing both short and long connections routing between PFUs.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.
LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There
are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.
Figure 2-6. Primary Clock Sources
From Routing
Clock Input
From Routing
PLL Input
Clock Input
PLL Input
PLL Input
Clock Input
PLL Input
From Routing
Clock Input
From Routing
PLL
PLL
PLL
PLL
20 Primary Clock Sources
To Quadrant Clock Selection
Note: Smaller devices have two PLLs.


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