MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 3

5/95

3Bit Differential FlipFlop

The MC10E/100E431 is a 3-bit flip-flop with differential clock, data

input and data output.

The asynchronous Set and Reset controls are edge-triggered rather

than level controlled. This allows the user to rapidly set or reset the

flip-flop and then continue clocking at the next clock edge, without the

necessity of de-asserting the set/reset signal (as would be the case with a

level controlled set/reset).

The E431 is also designed with larger internal swings, an approach

intended to minimize the time spent crossing the threshold region and

thus reduce the metastability susceptibility window.

The differential input structures are clamped so that the inputs of

unused registers can be left open without upsetting the bias network of

the device. The clamping action will assert the D and the CLK sides of the

inputs. Because of the edge triggered flip-flop nature of the device

simultaneously opening both the clock and data inputs will result in an

output which reaches an unidentified but valid state. Note that the input

clamps only operate when both inputs fall to 2.5V below VCC.

PIN NAMES

Pin

Function

D

[0:2], D[0:2]

Differential Data Inputs

CLK

[0:2], CLK[0:2]

Differential Clock

S

[0:2]

Edge Triggered Set Inputs

R

[0:2]

Edge Triggered Reset Input

VBB

VBB Reference Output

Q

[0:2], Q[0:2]

Differential Data Outputs

MC10E431

MC100E431

3-BIT DIFFERENTIAL

FLIP-FLOP

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

CLK0 CLK0

D0

D0

R0

D2

D2

CLK2

CLK2

VBB

VCCO

LOGIC DIAGRAM

CLK1

CLK1

R1

VEE

S1

D1

D1

26

27

28

2

3

4

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

5

6

7

8

9

10

R2

S2

Q2

Q2

VCC

Q1

Q1

Q0

Q0

S0

S0

D0

D0

CLK0

CLK0

R0

S1

D1

D1

CLK1

CLK1

R1

S2

D2

D2

CLK2

CLK2

R2

VBB

Q0

Q0

Q1

Q1

Q2

Q2

S

Q

R

Q

D

S

Q

R

Q

D

S

Q

R

Q

D

1

Pinout: 28-Lead PLCC (Top View)

* All VCC and VCCO pins are tied together on the die.