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MC100ELT25DR2 Folha de dados(PDF) 1 Page - ON Semiconductor

Nome de Peças MC100ELT25DR2
Descrição Electrónicos  Differential ECL to TTL Translator
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
Página de início  http://www.onsemi.com
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MC100ELT25DR2 Folha de dados(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 1999
February, 2000 – Rev. 3
1
Publication Order Number:
MC10ELT25/D
MC10ELT25, MC100ELT25
Differential ECL to TTL
Translator
The MC10ELT/100ELT25 is a differential ECL to TTL translator.
Because ECL levels are used a +5V, -5.2V (or -4.5V) and ground are
required. The small outline 8-lead SOIC package and the single gate of
the ELT25 makes it ideal for those applications where space,
performance and low power are at a premium. Because the mature
MOSAIC 1.5 process is used, low cost can be added to the list of
features.
The VBB output allows the ELT25 to also be used in a single-ended
input mode. In this mode the VBB output is tied to the IN input for a
non-inverting buffer or the IN input for an inverting buffer. If used the
VBB pin should be bypassed to ground via a 0.01µF capacitor.
The ELT25 is available in both ECL standards: the 10ELT is
compatible with MECL 10H logic levels while the 100ELT is
compatible with ECL 100K logic levels. For further information
regarding modeling, refer to AN1596/D “ECLinPS Lite Translator
ELT Family SPICE I/O Model Kit”.
2.6ns Typical Propagation Delay
Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
Q Output will default LOW with inputs open or at VEE
Differential ECL Inputs
Small Outline SOIC Package
24mA TTL Outputs
Flow Through Pinouts
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count: 135 devices
1
2
3
45
6
7
8
Q0
GND
VCC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D0
NC
D0
VBB
VEE
ECL
TTL
Device
Package
Shipping
ORDERING INFORMATION
MC10ELT25D
SO–8
98 Units / Rail
MC10ELT25DR2
SO–8
http://onsemi.com
2500 Units / Reel
PIN
FUNCTION
D
Diff ECL Inputs
Q
TTL Output
VCC
Positive Supply
VEE
Negative Supply
VBB
Reference Output
GND
Ground
PIN DESCRIPTION
MC100ELT25D
SO–8
98 Units / Rail
MC100ELT25DR2
SO–8
2500 Units / Reel
ALYW
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
HLT25
1
8
1
8
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
H = MC10
K = MC100
A = Assembly Location
ALYW
KLT25
1
8


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