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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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SLC90E66-UF Folha de dados(PDF) 9 Page - SMSC Corporation |
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SLC90E66-UF Folha de dados(HTML) 9 Page - SMSC Corporation |
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9 / 257 page  SMSC DS – SLC90E66 Page 9 Rev. 07/10/2002 8.7 SERIAL INTERRUPTS (SIRQ) ..........................................................................................................................171 8.7.1 SIRQ Protocol ....................................................................................................................................171 8.8 TIMER/COUNTERS.........................................................................................................................................173 8.8.1 Counter 0 ...........................................................................................................................................173 8.8.2 Counter 1 ...........................................................................................................................................173 8.8.3 Counter 2 ...........................................................................................................................................173 8.8.4 The Interval Timer Programming Interface.........................................................................................173 8.9 REAL TIME CLOCK MODULE ...........................................................................................................................175 8.9.1 RTC Registers and RAM....................................................................................................................175 8.9.2 Control Register A ..............................................................................................................................177 8.9.3 Control Register B ..............................................................................................................................178 8.9.4 Control Register C..............................................................................................................................179 8.9.5 Register D ..........................................................................................................................................179 8.9.6 RTC Update Cycle .............................................................................................................................179 8.9.7 RTC Interrupt .....................................................................................................................................180 8.9.8 Lockable RAM Ranges.......................................................................................................................180 8.9.9 RTC External Connections.................................................................................................................180 8.10 XBUS SUPPORT............................................................................................................................................180 8.11 STAND ALONE I/O APIC SUPPORT ................................................................................................................180 8.12 SYSTEM RESET LOGIC...................................................................................................................................181 8.13 HOST INTERFACE LOGIC ................................................................................................................................181 9.0 USB HOST CONTROLLER FUNCTIONAL OVERVIEW ..............................................................................182 9.1 HOST CONTROLLER DRIVER...........................................................................................................................182 9.1.1 Bandwidth Allocation ..........................................................................................................................183 9.1.2 List Management................................................................................................................................183 9.2 HOST CONTROLLER ......................................................................................................................................183 9.2.1 USB States.........................................................................................................................................183 9.2.2 Frame Management ...........................................................................................................................183 9.2.3 List Processing ...................................................................................................................................183 9.2.4 USB Power Management Functions ..................................................................................................184 10.0 IDE CONTROLLER FUNCTIONAL OVERVIEW...........................................................................................186 10.1 IDE CONFIGURATIONS...................................................................................................................................186 10.2 IDE REGISTER BLOCKS .................................................................................................................................186 10.2.1 Legacy Mode......................................................................................................................................186 10.2.2 PCI Native Mode ................................................................................................................................187 10.3 PIO IDE OPERATIONS...................................................................................................................................187 10.3.1 PIO IDE Data Transfer Cycle .............................................................................................................188 10.3.2 32-Bit PIO IDE Data Transfer Cycle ...................................................................................................188 10.3.3 PIO IDE Data Prefetching and Posting...............................................................................................188 10.4 BUS MASTER OPERATIONS ............................................................................................................................189 10.4.1 Physical Region Descriptor (PRD) .....................................................................................................189 10.4.2 Bus Master Transfer Operation ..........................................................................................................189 10.5 ULTRA ATA/66 SYNCHRONOUS DMA OPERATION ...........................................................................................190 10.5.1 Ultra ATA/66 Signals ..........................................................................................................................190 10.5.2 Ultra ATA/66 Operation ......................................................................................................................191 10.6 IDE DATA BUFFER ........................................................................................................................................192 11.0 POWER MANAGEMENT FUNCTIONAL OVERVIEW ..................................................................................193 11.1 SYSTEM CLOCK CONTROL .............................................................................................................................194 11.1.1 Host Clock Control .............................................................................................................................196 11.1.2 Stop Clock State Example Sequence.................................................................................................200 11.1.3 PCI Clock Control...............................................................................................................................202 11.2 PERIPHERAL DEVICE MANAGEMENT................................................................................................................203 11.2.1 Device Monitor and Idle Timer............................................................................................................203 11.2.2 Device Trap........................................................................................................................................204 11.2.3 Peripheral Device Management .........................................................................................................204 11.2.4 PCI/ISA Peripheral Devices ...............................................................................................................204 11.2.5 Device Specific Details.......................................................................................................................206 11.3 SUSPEND/RESUME CONTROL MECHANISM ......................................................................................................221 11.3.1 Suspend Modes .................................................................................................................................221 11.3.2 System Resume Mechanism..............................................................................................................222 11.3.3 Suspend and Resume Control Signaling............................................................................................223 11.3.4 Alternate AT Register Access Mode (Shadow Registers) ..................................................................240 |
Nº de peça semelhante - SLC90E66-UF |
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Descrição semelhante - SLC90E66-UF |
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