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FAN6520AIMX Folha de dados(PDF) 11 Page - Fairchild Semiconductor |
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FAN6520AIMX Folha de dados(HTML) 11 Page - Fairchild Semiconductor |
11 / 15 page PRODUCT SPECIFICATION FAN6520A REV. 1.0.2 8/26/04 11 Power MOSFET Selection For more information on MOSFET selection for synchro- nous buck regulators, refer to: AN-6005: Synchronous Buck MOSFET Loss Calculations. This Fairchild app note is located at: http://www.fairchildsemi.com/an/AN/AN-6005.pdf Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN6520A converter's output voltage is low with respect to its input voltage, therefore the lower MOSFET (Q2) is conducting the full load current for most of the cycle. Therefore choose a MOSFET for Q2 which has low RDS(ON) to minimize conduction losses. In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and its conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1’s primary selection criteria should be gate charge. High-Side Losses Figure 10 shows a MOSFET’s switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis, therefore, is also representative of gate charge (QG) . CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from the MOSFET’s datasheet. Assuming switching losses are about the same for both the rising edge and falling edge, Q1’s switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. These losses are given by: PUPPER = PSW + PCOND where: PUPPER is the upper MOSFET’s total losses, and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 (Figure 10). The driver’s impedance and CISS determine t2 while t3’s period is controlled by the driver’s impedance and QGD. Since most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS: Figure 10. Switching Losses and QG Figure 11. Drive Equivalent Circuit Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS – QTH where QTH is the gate charge required to get the MOSFET to its threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should also be taken to include the delivery of the MOSFET’s gate power (PGATE) in calculating the power dissipation required for the FAN6520A: PGATE = QG × VCC × FSW (17) where QG is the total gate charge to reach VCC. P SW V DS I L × 2 --------------------- 2 × t s × F SW = (14) P COND V OUT V IN -------------- I OUT 2 × R DS ON () × = (15) V SP t1 t2 t3 4.5V t4 t5 Q G(SW) V DS I D Q GS Q GD V TH V GS C ISS C GD C ISS C GD R D R GATE CGS HDRV 5V SW VIN G t s Q GSW () I DRIVER --------------------- Q GSW () VCC V SP – R DRIVER R GATE + ------------------------------------------------ ------------------------------------------------------ ≈≈ (16) |
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