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JN5189 Folha de dados(PDF) 13 Page - NXP Semiconductors |
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JN5189 Folha de dados(HTML) 13 Page - NXP Semiconductors |
13 / 92 page JN5189 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1.2 — June 2020 13 of 92 NXP Semiconductors IEEE 802.15.4 low power wireless MCU JN5189(T)/JN5188(T) 7.2 HVQFN40 - without NTAG 7.2.1 Pinning 7.2.2 Pin description (1) JN5188HN and JN5189HN HVQFN40 without NTAG Fig 3. Pin configuration aaa-023713 JN5188HN; JN5189HN 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 terminal 1 index area Transparent top view PIO7 PIO6 PIO5/ISP_ENTRY PIO1 XTAL_N XTAL_P PIO0 PIO3 PIO2 PIO4 PIO17/ADC3 PIO18/ADC4 TRST RSTN VBAT VSS(DCDC) LX PIO19/ADC5 PIO20/ACP PIO21/ACM Table 5. Pin descriptions Symbol Pin Type Default at reset Description XTAL_P 1 System crystal oscillator 32 MHz XTAL_N 2 System crystal oscillator 32 MHz PIO0 3 IO GPIO0[1] GPIO0 — General Purpose digital Input/Output 0 USART0_SCK — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - synchronous clock USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output PWM0 — Pulse Width Modulator output 0 SPI1_SCK — Serial Peripheral Interface-bus 1 clock input/output PDM0_DATA — Pulse Density Modulation Data input from digital microphone (channel 0) |
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