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BQ79600-Q1 Folha de dados(PDF) 60 Page - Texas Instruments

Nome de Peças BQ79600-Q1
Descrição Electrónicos  BQ79600-Q1 Automotive SPI/UART Communication Interface Functional-Safety Compliant With Automatic Host Wakeup
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10 Layout
The layout for this device must be designed carefully. Any design outside these guidelines can affect the
communication robustness and EMI performance. Care must be taken in the layout of signals to and from the
device to avoid coupling noise onto sensitive inputs. The layout of ground and power connections, as well as
communication signals, should also be made carefully.
10.1 Layout Guidelines
10.1.1 Ground Planes
It is very important to establish a clean grounding scheme to ensure best performance of the device. There is
one ground pin (GND) on the device. It is a good practice to use top and bottom PCB layers for signal routing,
and use middle layers as ground planes. Even on a PCB layer that is mainly for signal routing, it is good practice
to have a small island of ground pour if possible to provide a low-impedance ground, rather than simply a via
through the ground trace to an lower ground plane. Create a keep-out area (no other traces and no ground
plane) around the daisy chain components in all PCB layers.
There is a strong recommendation to have a minimum of 4 layers in the PCB, with one fully dedicated layer as
an unbroken VSS plane (except thermal reliefs). Avoid placing tracks on this layer to maintain the unbroken
integrity of the plane structure.
10.1.2 Bypass Capacitors for Power Supplies
The bypass capacitors of the following pins must be placed as close to the device pins as possible to ensure
proper performance.
• BAT, VIO, CVDD, DVDD
10.1.3 UART/SPI communication
The UART/SPI interface (MISO/TX, MOSI/RX, SCLK, nCS, nUART/SPI_RDY) between MCU and BQ79600-Q1
shall be kept as short and straight as possible for optimized EMC performance.
10.1.4 Daisy Chain Communication
It is important to have proper layout on the COMHP/N and COMLP/N circuits in order to have the best robust
daisy chain communication.
• Keep differential traces as short as possible and as straight as possible. Minimize turns and avoid any
looping on the traces.
• Keep the differential traces on the same layers. Run the trace in parallel with shielding and matching trace
impedance.
• Place the isolation components close to the connectors.
• Create a keep-out area (no other traces and no ground plane) around the daisy chain components in all PCB
layers.
10.2 Layout Example
This section presents the BQ79600-Q1 Evaluation Module (EVM) design as a layout example. Given the EVM
doesn't have an MCU, the example of UART/SPI connection layout is not optimized.
BQ79600-Q1
SLUSDS1A – NOVEMBER 2019 – REVISED AUGUST 2020
www.ti.com
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