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DRV8714-Q1 Folha de dados(PDF) 49 Page - Texas Instruments |
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DRV8714-Q1 Folha de dados(HTML) 49 Page - Texas Instruments |
49 / 144 page On H/W device variants, after the overtemperature condition is removed, the nFAULT pin is automatically cleared and the driver and charge pump automatically reenabled. 8.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC) The device provides the necessary hardware to conduct offline short circuit and open load diagnostics of the external power MOSFETs and load. This is accomplished by an integrated pull up and pull down current source on the SHx pin which connect to the external half-bridge switch-node. The offline diagnostics are controlled by the associated registers bits in the OLSC_CTRL register. First, the offline diagnostic mode needs to be enabled through the EN_OLSC register setting. Then the individual current sources can be enabled through the PD_SHx and PU_SHx register settings. The voltage on the SHx pin will be continuously monitored through the internal VDS comparators. During the diagnostic state the VDS comparators will report the real-time voltage feedback on the SHx pin node in the SPI registers in the associated VDS register status bit. When in the VDS comparators are in diagnostic mode, the global DS_GS SPI register bits will not report faults or warnings. Before enabling the offline diagnostics it is recommended to place the external MOSFET half-bridges in the disabled state through the EN_DRV register setting. Additionally, the VDS comparator threshold (VDS_LVL) should be adjusted to 1-V or greater to ensure enough headroom for the internal blocking diode forward voltage drop. On H/W device variants, this feature is not available. DRV SHx DRAIN VDS VDS PGND/SLx DRV8 SHy DRAIN VDS VDS PGND/SLy GHx GLx PU_SHx PU_SHy PD_SHy PD_SHx GHy GLy BDC Figure 8-28. Offline Diagnostics Note The VDS comparators will start real-time voltage feedback immediately after OLSC_EN is set. Feedback should be ignored until the proper pull up and pull down configuration is set. 8.3.8.13 Watchdog Timer The device integrates a programmable window type SPI watchdog timer to verify that the external controller is operating and the SPI bus integrity is monitored. The SPI watchdog timer can be enabled by through the WD_EN SPI register bit. The watchdog timer is disabled by default. When the watchdog timer is enabled, an internal timer starts to count up. The watcher dog timer is reset by inverting the WD_RST SPI register.. This WD_RST must be issued between the lower window time and the upper window time. If a watchdog timer fault is www.ti.com DRV8714-Q1, DRV8718-Q1 SLVSEA2 – AUGUST 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: DRV8714-Q1 DRV8718-Q1 |
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