SN74GTLP1395

TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS

WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

SCES349C – JUNE 2001 – REVISED NOVEMBER 2001

10

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR Y OUTPUTS

S1

Open

GND

500

Ω

500

Ω

TEST

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

S1

Open

6 V

GND

tPLH

tPHL

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

3 V

0 V

VOH

VOL

0 V

VOL + 0.3 V

VOH – 0.3 V

≈0 V

Input

3 V

3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(A input to B port)

Output

1.5 V

Test

Point

CL = 30 pF

(see Note A)

From Output

Under Test

12.5

Ω

LOAD CIRCUIT FOR B OUTPUTS

0 V

VOH

VOL

Input

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(B port to Y output)

Output

1.5 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

6 V

tPLH

tPHL

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1 V

1 V

1 V

1 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

(A input)

Figure 1. Load Circuits and Voltage Waveforms