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TC9325F Folha de dados(PDF) 6 Page - Toshiba Semiconductor

Nome de Peças TC9325F
Descrição Electrónicos  Single-Chip DTS Microcontroller (DTS-20)
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Fabricante Electrônico  TOSHIBA [Toshiba Semiconductor]
Página de início  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC9325F Folha de dados(HTML) 6 Page - Toshiba Semiconductor

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TC9325F
2002-05-14
6
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
61
62
63
64
P5-0/BUZR
P5-1
/SI3
P5-2
/SO3
/SO4
P5-3
/SCK3
/SCK4
I/O port 5
/buzzer output
/Serial data input 3
/Serial data
input/output 3
/Serial data
input/output 4
/Serial clock
input/output 3
/Serial clock
input/output 4
4-bit CMOS I/O ports.
Input and output can be programmed
in 1-bit unit.
Pin 5-0 is also used to output a buzzer
signal. Pins P5-1 to P5-3 are also
used to input/output the two serial
interface circuits (SIO3, SIO4).
The buzzer output can be selected
between eight frequency settings
(0.625 to 3 kHz), which can be output
in four modes: Continuous,
Single-Shot, 10 Hz-Intermittent, and
10-Hz Intermittent at 1-Hz Intervals.
SIO3 is a serial interface supporting
three lines, while the SIO4 serial
interface supports two lines.
On the clock edge of the SCK3/SCK4
pin, SIO3/SIO4 can input 4- or 8-bit
serial data to pin SI3 or output data to
the SO3/SO4 pin. As the serial
operating clock (SCK3/SCK4), an
internal (450/225/150/75 kHz) clock or
external clock can be selected. Rising
and falling shift can also be selected.
The clock data output is N-channel
open drain. This design facilitates LSI
control and communication between
controllers.
Enabling the SIO3 or SIO4 interrupts
triggers the interrupt and jumps the
program to address 3 when interface
SIO3 or SIO4 completes execution.
This is effective for high-speed serial
communications.
All of the input of SIO3 and SIO4
built-in the Schmitt circuits.
SIO3, SIO4, and their associated
controls can be used and set by
software.
65
MUTE
Muting output port
1-bit output port.
Normally used as a muting control
signal output. This pin can set the
internal MUTE bit to 1 according to
changes in the I/O port 8 input and
HOLD
input. The MUTE bit output
logic can be changed.
66
TEST
Test mode control
input
Input pin for controlling Test mode.
When the pins are at High level, the
device is in Test mode; at Low level,
in normal operation.
Normally, set the pins to Low level or
NC (pull-down resistors are
incorporated).
Input instruction
(P5-0)
VDD
Input instruction
+ SIOon
(P5-1~P5-3)
VDD
VDD
VDD
RIN2


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