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SN74BCT2420 Folha de dados(PDF) 1 Page - Texas Instruments |
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SN74BCT2420 Folha de dados(HTML) 1 Page - Texas Instruments |
1 / 12 page SN74BCT2420 NuBus ™ ADDRESS/DATA TRANSCEIVERS AND REGISTERS SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Copyright © 1989, Texas Instruments Incorporated 1 • Designed for NuBus™ Interface Applications • Conforms to ANSI/IEEE Std 1196-1987 • On-Chip Comparator Provides I/D Slot Identification • Multiplexed Real-Time and Latched Address/Data • Designed to Operate With SN74ACT2440 NuBus ™ Controller • BiCMOS Design Substantially Reduces Standby Current • Dependable Texas instruments Quality and Reliability description The ’BCT2420 consists of bus transceiver circuits, D-type flip-flops, latches, and control circuitry arranged for multiplexed transmission of address and data information in NuBus ™ applications. An on-chip comparator has been included to detect when a NuBus ™ transfer cycle is requesting the local board. The device conforms to ANSI/IEEE Std 1196-1987 and operates with Texas instru- ments SN74ACT2440 NuBus ™ Controller. In addition, the device is easily configured around ASIC or other PAL® -based controllers. The ’BCT2420 was designed using Texas Instruments BiCMOS process, which features bipolar drive characteristics and greatly reduces the standby power of the device when disabled. This feature is especially valuable when the device is not performing a NuBus ™ transaction. The AEN, DEN and ADEN inputs control the transceiver functions. Three 16-bit I/O ports, A15–A0, D15–D0, and AD15–AD0, provide for address and data transfer. When the NuBus ™ performs a write cycle to the local board, address information is saved on the rising edge of ACLK. During the last portion of the NuBus ™ write cycle, data information is saved on the rising edge of DCLK. When the local board is performing a write to the NuBus ™, address and data is multiplexed onto the NuBus™ via the A/D line. Address and data can be latched by using the ALE and DLE input lines respectively. The IDEQ output is used to signal that the local board is being requested by the NuBus ™. This output is typically fed to the NuBus ™ controller. IDEQ goes active (low) when AD15–AD12 are low and AD11–AD8 match ID3–ID0. IDEQ stays valid until the next address clock (ACLK) occurs. Internal 10-k Ω pullup resistors are included on the ID3–ID0 inputs. The SSEQ output is used to signal the local board that super-slot addresses are being requested. This output is active (low) whenever AD15–AD12 are equal to ID3–AD0, except when ID3–ID0 are all low. In typical NuBus ™ applications, two devices are required to provide the full 32-bit address/data path. Refer to the typical NuBus ™ interface diagram on page 9 for additional information. The SN74BCT2420 is characterized for operation from 0 °C to 70°C. NuBus is a trademark of Texas Instruments Incorporated. PAL is a registered trademark of Monolithic Memories Inc. 27 28 29 ID0 ALE IDEQ VCC AD15 AD14 AD13 AD12 GND AD11 AD10 AD9 AD8 ID1 ADEN DCLK ID2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AEN ACLK ID3 SSEQ AD7 AD6 AD5 AD4 GND AD3 AD2 AD1 AD0 VCC A/D DLE DEN 31 32 33 34 FN PACKAGE (TOP VIEW) 87 6 5 4 93 168 67 2 3536 37 38 39 66 65 64 63 62 61 40 41 42 43 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Nº de peça semelhante - SN74BCT2420 |
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Descrição semelhante - SN74BCT2420 |
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