T E C H NI CA L INFO RMA T IO N
9
When the voltage drop becomes greater than V
OC-LIMIT
(approximately 0.7V) the TA2021-100 will
try to limit the current by internally decreasing the gain of the input stage of the TA2021-100.
If the voltage drop continues to increase to greater than V
OC-SD (approximately 1.2V) the TA2021-
100 will shut off the output stages of its amplifiers and supply a logic level high on
HMUTE/SDA. The occurrence of an over-current condition is latched in the TA2021-100 and can
be cleared by toggling the MUTE input or cycling power.
Mute
When a logic high signal is supplied to MUTE, both amplifier channels are muted (both high-
and low-side transistors are turned off) and a logic level high is output on the HMUTE/SDA pin.
When a logic level low is supplied to MUTE, both amplifiers are fully operational and a logic
level low is supplied on HMUTE/SDA.
There is a delay of approximately 200 milliseconds
between the de-assertion of MUTE and the un-muting of the TA2021-100.
Mute-in-silence
The TA2021-100 will automatically mute both channels when the sum of the audio signal
supplied to both of its inputs is below a preset level for approximately 340 seconds. The preset
audio level is determined by the voltage on the MIS/ADDR pin according to the following table
(The MIS/ADDR pin also determines the input-limit level, as described in the next section):
MIS/ADDR Pin Voltage
(Fraction of V5)
MIS Level
Input-limit Level
0.00 – 0.05
-80dB
76%
0.05 – 0.10
-80dB
79%
0.10 – 0.15
-80dB
85%
0.15 – 0.20
-80dB
100%
0.20 – 0.25
-74dB
76%
0.25 – 0.30
-74dB
79%
0.30 – 0.35
-74dB
85%
0.35 – 0.40
-74dB
100%
0.40 – 0.45
-68dB
75%
0.45 – 0.50
-68dB
79%
0.50 – 0.55
-68dB
85%
0.55 – 0.60
-68dB
100%
0.60 – 0.65
-62dB
75%
0.65 – 0.70
-62dB
79%
0.70 – 0.75
-62dB
85%
0.75 – 0.80
-62dB
100%
0.80 – 0.85
MIS Off
75%
0.85 – 0.90
MIS Off
79%
0.90 – 0.95
MIS Off
85%
0.95 – 1.00
MIS Off
100%
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