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ICS527-03 Folha de dados(PDF) 1 Page - Integrated Circuit Systems |
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ICS527-03 Folha de dados(HTML) 1 Page - Integrated Circuit Systems |
1 / 8 page ICS527-03 MDS 527-03 B 1 Revision 122804 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com Clock Slicer User Configurable PECL Output Zero Delay Buffer Preliminary Information Description The ICS527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-03 aligns rising edges on CLKIN with FBPECL at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the ICS527-04. Features • Packaged as 28 pin SSOP (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Input clock frequency of 1.5 MHz to 200 MHz • Output clock frequencies from 2.5 MHz to 160 MHz • Very low jitter • Duty cycle of 45/55 • Operating voltage of 3.3 V • Advanced, low power CMOS process Block Diagram PECL VDD GND 2 2 Reference Divider Phase Comparator, Charge Pump, and Loop Filter VCO Output Divider 7 7 2 R6:R0 F6:F0 S1:S0 PDTS Feedback Divider FBPECL FBPECL PECL CLKIN 1 0 Divide by 2 1 0 Divide by 2 DIV2 68 ohm 180 ohm 68 ohm 180 ohm VDD VDD |
Nº de peça semelhante - ICS527-03 |
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Descrição semelhante - ICS527-03 |
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