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KM68B261A-6 Folha de dados(PDF) 5 Page - Samsung semiconductor |
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KM68B261A-6 Folha de dados(HTML) 5 Page - Samsung semiconductor |
5 / 7 page KM68B261A BiCMOS SRAM Rev 2.0 October-1994 5 TIMING DIAGRAMS TIMING WAVE FORM OF READ CYCLE (/WE=VIH) NOTES (READ CYCLE) /WE is high for read cycle. All read cycle timing is referenced from the last valid address to the first transition address. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. Transition is measured ± 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. Device is continuously selected with /CS=VIL Address valid prior to coincident with /CS transition low. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. Address /CS /OE Data Out Data Valid High-Z tCO tOH tRC tAA tOE tOLZ t LZ (4,5) tOHZ t HZ(3,4,5) 1. 2. 3. 4. 5. 6. 7. 8. Address /CS /WE Data In TIMING WAVE FORM OF WRITE CYCLE(1) (/OE=Clock) High-Z tCW(3) tDH tRC tAW Data Valid t WP(2) t WR(5) tOW High-Z(8) tOHZ(6) tAS(4) tDW /OE Data Out |
Nº de peça semelhante - KM68B261A-6 |
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Descrição semelhante - KM68B261A-6 |
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