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ML2240 Folha de dados(PDF) 4 Page - OKI electronic componets

Nome de Peças ML2240
Descrição Electrónicos  4-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI
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Fabricante Electrônico  OKI [OKI electronic componets]
Página de início  http://www.oki.com
Logo OKI - OKI electronic componets

ML2240 Folha de dados(HTML) 4 Page - OKI electronic componets

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FEDL2240DIGEST-02
OKI Semiconductor
ML2240 Family
4/24
PIN DESCRIPTIONS
80-pin Plastic TQFP
Pin
Symbol
Type
Description
1-3, 5, 66-68,
73-80
RD14-RD0
I
Data pins to connect an external memory.
Data is input when the
ROE pin is at "L" level. Input data from outside
is not accepted when the
ROE pin is at "H" level. The RD14-RD8 pins
do not accept input data from outside when the
BYTE pin is at "L"
level.
6
RD15/A-1
I/O
Data pin of the externally connected memory when
BYTE pin is at “H”
level.
The data is input when the
ROE pin output is at "L" level. When the
ROE pin output is at "H" level, input data from outside is not accepted.
This pin becomes an address A-1 output pin when the device is in byte
mode. The address is output when the
RCS pin is at "L" level. When
the
RCS pin is at "H" level, this pin is in a high impedance state.
7
BYTE
I
Word/byte switching pin of the externally connected memory.
When
BYTE pin = “L” level: Byte mode
When
BYTE pin = “H” level: Word mode
8-20, 22-24,
28-30, 32-35
RA22-RA0
O
Address pins of an externally connected memory.
When
RCS pin = “H”: High impedance
25
XT
I
Wired to a crystal or ceramic oscillator.
Contains a feedback resistor of around 1 M
Ω between this XT pin and
XT pin (pin 27).
When using an external clock, input the clock from this pin.
27
XT
O
Wired to a crystal or ceramic oscillator.
When using an external clock, keep this pin open.
36
RESET
I
When “L” level is input to this pin, the device is reset to the initial state.
The oscillation stops, and AOUT output goes into “GND” level.
37
WR
I
CPU interface write signal.
When
CS pin is at “H” level, the WR signal cannot be input to the
device.
38
RD
I
CPU interface read signal.
For parallel input interface, a status signal for each channel is output
from the D0-D7 pins when the
RD pin is at "L" level. For the serial
input interface, a status signal for each channel is output from the
D5/D0 pin. This pin has a pull-up resistor built-in.
39
CS
I
CPU interface chip select pin.
When
CS pin is at “H” level, the WR, and RD signals cannot be input to
the device.
41-44
D3/STA3
D2/STA2
D1/STA1
D0/STA0
I/O
CPU interface data bus pins in the parallel input interface become
data input pins when
WR is at “L” level.
They become channel status output pins in the serial input interface.
These pins also become channel status output pins when
RD is at “L”
level.


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