DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Final
7
Version: DM9101-DS-F03
July 22, 1999
Pin Description (continued)
Pin No.
Pin Name
I/O
Description
LQFP
QFP
LED Interface :
These outputs can directly drive LEDs or provide status information to a network management device.
48
50
FDXLED#
(POLLED)
O
Polarity/Full Duplex LED:
Indicates Full Duplex mode status for 100Mbps and 10Mbps
operation (Active low). If bit 4 of Register 16 (FDXLED_MODE) is
set, the FDXLED# pin function will change to indicate the Polarity
status for 10Mbps operation. If polarity is inverted, the POLLED
will go ON.
49
51
COLLED#
O
Collision LED:
Indicates the presence of collision activity for 10Mbps and
100Mbps operation. This LED has no meaning for 10Mbps or
100Mbps Full Duplex operation (Active low).
51
53
LINKLED#
(TRAFFIC
LED)
O
Link LED:
Indicates Good Link status for 10Mbps and 100Mbps operation
(Active low).
It functions as the TRAFFIC LED when bit 5 of register 16 is set
to 1. In TRAFFIC LED mode, it is always ON when the link is OK.
The TRAFFIC LED flashes when transmitting or receiving.
52
54
RXLED#
OD
Receive LED:
Indicates the presence of receive activity for 10Mbps and
100Mbps operation (Active low).
The DM9101 incorporates a "monostable" function on the RXLED
output. This ensures that even minimal receive activity will
generate an adequate LED ON time.
53
55
TXLED#
OD
Transmit LED:
Indicates the presence of transmit activity for 10Mbps and
100Mbps operation (Active low).
The DM9101 incorporates a "monostable" function on the TXLED
output. This ensures that even minimal transmit activity will
generate an adequate LED ON time.
Device Configuration/Control/Status Interface
40
42
UTP
O
UTP Cable Indication:
UTP=1: Indicates UTP cable is used.
41
43
SPEED10
O
Speed 10Mbps:
When set high, this bit indicates a 10Mbps operation, when set
low 100Mbps operation. This pin can drive a low current LED to
indicate that 100Mbps operation is selected.
42
44
RX_LOCK
O
Lock for Clock/Data Recovery PLL:
When this pin is high it indicates that the receiver recovery PLL
logic has locked to the input data stream.
45
47
LINKSTS
O
Link Status Register Bit:
This pin reflects the status of bit 2 register 1.
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