CAT24C03

3

Doc No. 1113, Rev. A

© 2006 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

A.C. CHARACTERISTICS

Symbol

Parameter

1.8 V - 5.5 V

2.5 V - 5.5 V

Units

Min

Max

Min

Max

Clock Frequency

100

400

kHz

Noise Suppression Time Constant at

SCL, SDA Inputs

0.1

0.1

μs

SCL Low to SDA Data Out

3.5

0.9

μs

Time the Bus Must be Free Before a

New Transmission Can Start

4.7

1.3

μs

Start Condition Hold Time

4

0.6

μs

Clock Low Period

4.7

1.3

μs

Clock High Period

4

0.6

μs

Start Condition Setup Time

4.7

0.6

μs

Data In Hold Time

0

0

μs

Data In Setup Time

0.25

0.1

μs

SDA and SCL Rise Time

1

0.3

μs

SDA and SCL Fall Time

0.3

0.3

μs

Stop Condition Setup Time

4

0.6

μs

Data Out Hold Time

0.1

0.1

μs

Write Cycle Time

5

5

ms

Power-up to Ready Mode

1

1

ms

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/O

Power-On Reset (POR)

The CAT24C03 incorporates Power-On Reset (POR)

circuitry which protects the internal logic against

powering up in the wrong state.

The CAT24C03 will power up into Standby mode after

trigger level. This bi-directional POR feature protects

the device against ‘brown-out’ failure following a

temporary loss of power.

required for proper initialization of the internal state

machines. The POR trigger level automatically tracks the

internal CMOS device thresholds, and is naturally well