Rev: 1.00 6/2003

7/30

© 2003, GSI Technology, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8330LW36/72C-250/200

Two Byte Write Control Example with Late Write SigmaRAM

Special Functions

Burst Cycles

SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations.

The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter

generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM

by driving the ADV pin low, into Load mode.

DA

DB

DE

DA

DC

F

Write

BC

D

ADV

ADV

Non-Write

Write

Write

CK

Address

A

E

Write

CQ

/BA

/BB

DQA0-DQA8

DQB0-DQB8