Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

GS8321E18GE-150IV Folha de dados(PDF) 1 Page - GSI Technology

Nome de Peças GS8321E18GE-150IV
Descrição Electrónicos  2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  GSI [GSI Technology]
Página de início  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8321E18GE-150IV Folha de dados(HTML) 1 Page - GSI Technology

  GS8321E18GE-150IV Datasheet HTML 1Page - GSI Technology GS8321E18GE-150IV Datasheet HTML 2Page - GSI Technology GS8321E18GE-150IV Datasheet HTML 3Page - GSI Technology GS8321E18GE-150IV Datasheet HTML 4Page - GSI Technology GS8321E18GE-150IV Datasheet HTML 5Page - GSI Technology GS8321E18GE-150IV Datasheet HTML 6Page - GSI Technology GS8321E18GE-150IV Datasheet HTML 7Page - GSI Technology GS8321E18GE-150IV Datasheet HTML 8Page - GSI Technology GS8321E18GE-150IV Datasheet HTML 9Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 31 page
background image
GS8321E18/32/36E-xxxV
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz–133 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
165-Bump FP-BGA
Commercial Temp
Industrial Temp
Rev: 1.04 6/2006
1/31
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
Functional Description
Applications
The GS8321E18/32/36E-xxxV is a 37,748,736-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK3). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be
initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not be
used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
DCD Pipelined Reads
The GS8321E18/32/36E-xxxV is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8321E18/32/36E-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 1.8 V or 2.5 Vcompatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
3.0
4.0
3.0
4.4
3.0
5.0
3.5
6.0
3.8
6.6
4.0
7.5
ns
ns
Curr (x18)
Curr (x32/x36)
285
330
250
290
215
255
200
235
190
220
165
195
mA
mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
Curr (x18)
Curr (x32/x36)
205
235
195
225
185
210
175
200
165
190
155
175
mA
mA


Nº de peça semelhante - GS8321E18GE-150IV

Fabricante ElectrônicoNome de PeçasFolha de dadosDescrição Electrónicos
logo
GSI Technology
GS8321E18GE-150I GSI-GS8321E18GE-150I Datasheet
994Kb / 34P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
More results

Descrição semelhante - GS8321E18GE-150IV

Fabricante ElectrônicoNome de PeçasFolha de dadosDescrição Electrónicos
logo
GSI Technology
GS832118E GSI-GS832118E Datasheet
1,004Kb / 32P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832018 GSI-GS832018 Datasheet
669Kb / 25P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8321E18E GSI-GS8321E18E Datasheet
994Kb / 34P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8321EV18E GSI-GS8321EV18E Datasheet
978Kb / 33P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832018T-V GSI-GS832018T-V Datasheet
1Mb / 24P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320EV18T GSI-GS8320EV18T Datasheet
630Kb / 24P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320E18T-V GSI-GS8320E18T-V Datasheet
1Mb / 24P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832036AGT-250I GSI-GS832036AGT-250I Datasheet
253Kb / 24P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832118E-V GSI-GS832118E-V Datasheet
1Mb / 31P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8321V18E GSI-GS8321V18E Datasheet
988Kb / 31P
   2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


Folha de dados Download

Go To PDF Page


Ligação URL




Privacy Policy
ALLDATASHEETPT.COM
ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com