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74ABT843PW Folha de dados(PDF) 2 Page - NXP Semiconductors

Nome de Peças 74ABT843PW
Descrição Electrónicos  9-bit interface latch with set and reset 3-State
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Fabricante Electrônico  PHILIPS [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ABT843PW Folha de dados(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
2
1998 Jan 16
853-1620 18864
FEATURES
High speed parallel latches
Extra data width for wide address/data paths or buses carrying
parity
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Slim DIP 300 mil package
Broadside pinout
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Power-up 3-State
Power-up reset
DESCRIPTION
The 74ABT843 Bus interface latch is designed to eliminate the extra
packages required to buffer existing registers and provide extra data
width for wider data/address paths of buses carrying parity.
The 74ABT843 consists of nine D-type latches with 3-State outputs.
In addition to the LE and OE pins, it has a Master Reset (MR) pin
and Preset (PRE) pin. These pins are ideal for parity bus interfacing
in high performance systems. When MR is Low, the outputs are Low
if OE is Low. When MR is High, data can be entered into the latch.
When PRE is Low, the outputs are High, if OE is Low. PRE
overrides MR.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
Dn to Qn
CL = 50pF; VCC = 5V
5.0
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
COUT
Output capacitance
Outputs disabled;
VO = 0V or VCC
7
pF
ICCZ
Total supply current
Outputs disabled; VCC = 5.5V
500
nA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
–40
°C to +85°C
74ABT843 N
74ABT843 N
SOT222-1
24-Pin plastic SO
–40
°C to +85°C
74ABT843 D
74ABT843 D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +85°C
74ABT843 DB
74ABT843 DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +85°C
74ABT843 PW
74ABT843PW DH
SOT355-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21
22
23
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
Q7
D8
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
Q8
11
14
MR
PRE
12
13
GND
LE
TOP VIEW
SA00250
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input
(active-Low)
2, 3, 4, 5, 6,
7, 8, 9, 10
D0-D8
Data inputs
23, 22, 21, 20,
19,18, 17, 16, 15
Q0-Q8
Data outputs
11
MR
Master reset input (active-Low)
13
LE
Latch enable input (active rising
edge)
14
PRE
Preset input (active-Low)
12
GND
Ground (0V)
24
VCC
Positive supply voltage


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