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74ALS373N Folha de dados(PDF) 2 Page - NXP Semiconductors |
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74ALS373N Folha de dados(HTML) 2 Page - NXP Semiconductors |
2 / 13 page Philips Semiconductors Product specification 74ALS373/74ALS374 Latch/flip-flop 74ALS373 Octal transparent latch (3-State) 74ALS374 Octal D flip-flop (3-State) 2 1991 Feb 08 853–1243 01670 FEATURES • 8-bit transparent latch – 74ALS373 • 8-bit positive edge triggered register – 74ALS374 • 3-State output buffers • Common 3-State output register • Independent register and 3-State buffer operation TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74ALS373 6.0ns 14mA TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74ALS374 50MHz 17mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 20-pin plastic DIP 74ALS373N, 74ALS374N SOT146-1 20-pin plastic SOL 74ALS373D, 74ALS374D SOT163-1 20-pin plastic SSOP Type II 74ALS373DB, 74ALS374DB SOT339-1 DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output. When OE is High, the outputs are in High impedance “off” state, which means they will neither drive nor load the bus. The 74ALS374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low output enable (OE) controls all eight 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in High impedance “off” state, which means they will neither drive nor load the bus. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 – D7 Data inputs 1.0/1.0 20 µA/0.1mA E (74ALS373) Enable input (active-High) 1.0/1.0 20 µA/0.1mA OE Output enable inputs (active-Low) 1.0/1.0 20 µA/0.1mA CP (74ALS374) Clock pulse input (active rising edge) 1.0/1.0 20 µA/0.1mA Q0 – Q7 3-State outputs 130/240 2.6mA/24mA NOTE: One (1.0) ALS unit load is defined as: 20 µA in the High state and 0.1mA in the Low state. |
Nº de peça semelhante - 74ALS373N |
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Descrição semelhante - 74ALS373N |
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